Characterization of Supply and Substrate Noises in CMOS Digital Circuits

Abstract

The biggest contributors to the substrate noise are supply noises, since the power and ground wires are directly connected to the silicon substrate for CMOS digital cells. Clock trees in large digital designs can acquire large power consumption when thousands of flip-flops transitioning through the switching zone. Memories also draw significant instantaneous power when being accessed. In this paper, a measurement of the substrate noise in conjunction with the supply noises analyses were conducted on a real circuit system. The measured substrate noise waveforms were proportional to the power consumptions and substantially correlated with the supply noises for each test condition. As a result, these observations could be useful for modeling substrate noise effects and developing prevention methods.