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2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS 在90纳米CMOS 1V 10位400MS/s电流转向D/A转换器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373232
Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, W. Huang
{"title":"A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS","authors":"Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, W. Huang","doi":"10.1109/VDAT.2007.373232","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373232","url":null,"abstract":"This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130717836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Digital Envelope Modulator for an OFDM WLAN Polar Transmitter in 90 nm CMOS 用于90nm CMOS OFDM WLAN极性发射机的数字包络调制器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373242
P. van Zeijl, M. Collados
{"title":"A Digital Envelope Modulator for an OFDM WLAN Polar Transmitter in 90 nm CMOS","authors":"P. van Zeijl, M. Collados","doi":"10.1109/VDAT.2007.373242","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373242","url":null,"abstract":"A digital envelope modulator for an OFDM WLAN polar transmitter has been designed in 90 nm digital CMOS process for the 802.11 a/b/g standards. The digital modulator reaches an output power of -5 dBm for 54 Mbit/s using 64 QAM and fulfilling EVM specifications and in-band spectral mask requirements using 12.7 mW from a 1.2 V supply. When the digital modulator is combined with an off-chip PA, the output power increases to 20.4 dBm, while still fulfilling EVM specifications and in-band spectral mask requirements.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122206479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Efficient Calculation of Timed Cumulative Probability Density Function 时间累积概率密度函数的有效计算
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373252
Yu-Shih Su, Y. Weng, Shih-Chieh Chang
{"title":"Efficient Calculation of Timed Cumulative Probability Density Function","authors":"Yu-Shih Su, Y. Weng, Shih-Chieh Chang","doi":"10.1109/VDAT.2007.373252","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373252","url":null,"abstract":"It is well known that critical paths of a design are rarely activated because sensitization of long paths requires appropriate values applied at appropriate time for many gates. Several researches use the concept of rare activation for performance optimization but they require the accurate probability information of rare activation. We define timed cumulative probability density function (Timed-CDF) to be the probability distribution of a circuit's delay induced by input patterns. Because a Timed-CDF is very useful for many applications, in this paper, we present an efficient way for constructing a Timed-CDF. Our basic idea utilizes a concept called timed characteristic function, which allows us to perform very fast parallel simulation rather than the traditional event-driven simulation. On average, our results are 6.18 times faster then the traditional simulation.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Realization of Low Noise Silicon Acoustic Transducer Interface Circuit 低噪声硅声换能器接口电路的实现
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.372762
Yu-Chun Hsu, Wen-Chieh Chou, L. Liao, J. Tsai
{"title":"A Realization of Low Noise Silicon Acoustic Transducer Interface Circuit","authors":"Yu-Chun Hsu, Wen-Chieh Chou, L. Liao, J. Tsai","doi":"10.1109/VDAT.2007.372762","DOIUrl":"https://doi.org/10.1109/VDAT.2007.372762","url":null,"abstract":"An interface circuit dedicated for silicon acoustic transducer is presented. The circuit includes a transimpedance amplifier for the impedance matching between the acoustic sensor and the negative feedback amplifier along with a negative feedback amplifier with a fixed gain for pre-amplifying the acoustic signal. The input stage of the negative feedback amplifier is specially designed to satisfy sensor's specifications and avoid low frequency noise. The circuit is implemented in a standard CMOS process, and measurements with a conventional silicon microphone are taken. The interface circuit achieves 20dB gain, and a SNR of 51dB with an A-weighted output noise of-119dBV. Results shown in this article validates the circuit designed.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120924831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H) 数字视频广播(DVB-T/H)高效内存FFT架构
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373250
C. Wey, Wei-Chien Tang, Shin-Yo Lin
{"title":"Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H)","authors":"C. Wey, Wei-Chien Tang, Shin-Yo Lin","doi":"10.1109/VDAT.2007.373250","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373250","url":null,"abstract":"An efficient FFT (fast Fourier transform) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This study developed four types of efficient memory-based Radix-2 FFT architecture with a memory size of N words for N-point FFT operations. The latency can be improved from (N/2)+(N/ 2)logN, to (N/2+2)+(N/4)logN, further to [N/2+2]+(N/8) logN, at the cost of increased hardware. Results show that the developed parallel memory-based architecture can achieve a latency of 140 us with 2.425 mm2 in area for N=8192, which is well suitable for being implemented in DVB-T/H.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132128844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance Per Watt Microprocessor 芯片功率表征、验证和调试的后硅设计方法应用于高性能每瓦微处理器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373233
Y.-C.S. Chen, D. Lu, Gang Yuan
{"title":"Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance Per Watt Microprocessor","authors":"Y.-C.S. Chen, D. Lu, Gang Yuan","doi":"10.1109/VDAT.2007.373233","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373233","url":null,"abstract":"As performance per Watt concept being adapted on CPU's performance, a comprehensive post-silicon design methodology on chip power characterization, debug, and validation developed for an energy-efficient product performance become ever more important. An infrared photon-emission (IREM) based technique has been established to meet the needs. With those developed tool capabilities, we can validate simulated fullchip power, determine the causes of excessive power leakage, generate die power and thermal maps, and eventually optimize follow-on designs for power performance. This newly developed techniques have been applied and proven reusable on multiple core microprocessors fabricated under 90 nm and 65 nm CMOS technology. Examples of 5-8% power saving as compared with the first silicon data are presented here to demonstrate the success on debug and design optimization on full chip power.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126157732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Generalized MLP/BP-based MIMO DFEs for Overcoming ISI and ACI in Band-limited Channels 基于广义MLP/ bp的MIMO DFEs克服带限信道中ISI和ACI
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373221
Terng-Ren Hsu, Chi-Shi Chen, Terng-Yin Hsu, Chen-Yi Lee
{"title":"Generalized MLP/BP-based MIMO DFEs for Overcoming ISI and ACI in Band-limited Channels","authors":"Terng-Ren Hsu, Chi-Shi Chen, Terng-Yin Hsu, Chen-Yi Lee","doi":"10.1109/VDAT.2007.373221","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373221","url":null,"abstract":"In this work, we base on generalized multi-layered perceptron neural networks with backpropagation algorithm (generalized MLP/BP) to construct multi-input multi-output (MIMO) decision feedback equalizers (DFEs). The proposal is used to recover distorted nonreturn-to-zero (NRZ) data in wireline parallel band-limited channels. From the simulations, we note that the proposed design can recover severe distorted NRZ data as well as suppress intersymbol interference (ISI), adjacent channel interference (ACI) and background noise. The better BER performance as compared to a set of LMS DFEs and an MLP/BP-based MIMO DFE is achieved in the wireline parallel band-limited channels where the data rate is ten times as much as the channel bandwidth.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125801175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Matching-based Placement and Routing System for Analog Design 一种基于匹配的模拟设计布线系统
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373200
Po-Hung Lin, Ho-Che Yu, Tian-Hau Tsai, Shyh-Chang Lin
{"title":"A Matching-based Placement and Routing System for Analog Design","authors":"Po-Hung Lin, Ho-Che Yu, Tian-Hau Tsai, Shyh-Chang Lin","doi":"10.1109/VDAT.2007.373200","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373200","url":null,"abstract":"Matching placement and routing is very important in layout design of high performance analog circuits. This paper presents a matching-based placement and routing system for custom layout design automation especially for analog or mixed-signal designs. The system explores various device-level matching-placement and matching-routing patterns to generate the most compact and high-quality layouts. Inputting a circuit netlist, the system automatically analyzes the circuit and extracts matching devices to form several matching device groups. Then, it selects the best matching placement and routing pattern for each device or device group to optimize and to meet the overall placement objectives and constraints. All patterns are user-configurable, stored in the pattern database, and portable from design to design. After the layout of each device and device group is generated and placed, the constraint-driven shape-based router is invoked to complete the layout. The overall system can easily generate high-quality layouts and greatly reduce the layout design time.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1999 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128255749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Automation of Synchronous Bias Transmission Line Pulsing System 同步偏置传输线脉冲系统的自动化
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373254
Bor-Wei Chang, Hsin-Chyh Hsu, M. Ker
{"title":"Automation of Synchronous Bias Transmission Line Pulsing System","authors":"Bor-Wei Chang, Hsin-Chyh Hsu, M. Ker","doi":"10.1109/VDAT.2007.373254","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373254","url":null,"abstract":"Synchronous bias transmission line pulsing (SB-TLP) system is able to provide a synchronous bias voltage to transmission line pulse. It's a more useful test bench to evaluate actual circuit characteristics of electrostatic discharge (ESD) protection design with gate-driven mechanism than traditional Transmission Line Pulsing (TLP) system. It's important to set up an automatic SB-TLP system and be able to immediately analyze measured data which is more convenient to engineers. All of the instruments are controlled by a software written in LabVIEW environment to create a smart and friendly test workbench.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128904863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test Power IR Drop Closure Flow for NetComposer-I Platform Design NetComposer-I平台设计的测试电源IR跌落闭合流程
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373201
A. Kifli, W.J. Chen, Y.W. Chen, K.C. Wu
{"title":"Test Power IR Drop Closure Flow for NetComposer-I Platform Design","authors":"A. Kifli, W.J. Chen, Y.W. Chen, K.C. Wu","doi":"10.1109/VDAT.2007.373201","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373201","url":null,"abstract":"Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128922142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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