NetComposer-I平台设计的测试电源IR跌落闭合流程

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI:10.1109/VDAT.2007.373201

A. Kifli, W.J. Chen, Y.W. Chen, K.C. Wu

{"title":"NetComposer-I平台设计的测试电源IR跌落闭合流程","authors":"A. Kifli, W.J. Chen, Y.W. Chen, K.C. Wu","doi":"10.1109/VDAT.2007.373201","DOIUrl":null,"url":null,"abstract":"Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Test Power IR Drop Closure Flow for NetComposer-I Platform Design\",\"authors\":\"A. Kifli, W.J. Chen, Y.W. Chen, K.C. Wu\",\"doi\":\"10.1109/VDAT.2007.373201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test.\",\"PeriodicalId\":137915,\"journal\":{\"name\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2007.373201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2007.373201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

功率噪声已成为SoC设计中失败芯片的主要罪魁祸首之一。由于扫描测试过程中的功耗可能比正常运行时高几倍，因此必须在实施和测试阶段妥善处理。在本文中，我们分享了我们在开发NetComposer平台设计过程中所获得的一些与测试能力相关的经验。我们演示了良好的功率分析和DFT如何帮助避免测试过程中潜在的功率噪声问题。

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Test Power IR Drop Closure Flow for NetComposer-I Platform Design

Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test.

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2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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