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2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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A LC-Tank Injection Locked Frequency Divider with Complementary Structure 互补结构的LC-Tank注入锁定分频器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373248
Shao-Hua Lee, S. Jang, Jian-Feng Lee, Yun-Hsueh Chung, Huang-Mei Chen
{"title":"A LC-Tank Injection Locked Frequency Divider with Complementary Structure","authors":"Shao-Hua Lee, S. Jang, Jian-Feng Lee, Yun-Hsueh Chung, Huang-Mei Chen","doi":"10.1109/VDAT.2007.373248","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373248","url":null,"abstract":"This paper presents a LC-tank injection locked frequency divider with Complementary structure. The frequency divider is implemented using a standard UMC 0.18-mum CMOS process. The proposed circuit adds an injection nMOS transistor between the differential outputs of the frequency divider with the structure of complementary VCO that contains a tapped LC resonator. The measurement results show that at the supply voltage of 1.2V. the divider free-running frequency is tunable from 1.86-GHz to 2.31-GHz, the locking range in divide-by-2 mode is about 1.52-GHz (35.7%), and the locking range in the divide-by-4 mode is about 2.05-GHz (24.4%). The core power consumption is 4.08mW.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122445795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware Architecture Design of CABAC Codec for H.264/AVC H.264/AVC的CABAC编解码器硬件体系结构设计
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373257
Lingfeng Li, Yang Song, T. Ikenaga, S. Goto
{"title":"Hardware Architecture Design of CABAC Codec for H.264/AVC","authors":"Lingfeng Li, Yang Song, T. Ikenaga, S. Goto","doi":"10.1109/VDAT.2007.373257","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373257","url":null,"abstract":"This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0.18 mum technology. Results show that the equivalent gate counts is 33.2 k when the maximum frequency is 230 MHz. It is estimated that the proposed CABAC codec can process the input binary symbol at 135 Mb/s for encoding and 90 Mb/s for decoding.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"54 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116657809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Input Selection Encoding for Low Power Multiplexer Tree 低功率复用器树的输入选择编码
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373253
Hsiao-En Chang, Juinn-Dar Huang, Chia-I Chen
{"title":"Input Selection Encoding for Low Power Multiplexer Tree","authors":"Hsiao-En Chang, Juinn-Dar Huang, Chia-I Chen","doi":"10.1109/VDAT.2007.373253","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373253","url":null,"abstract":"With the advent of portable devices, power consumption becomes one of the most important considerations in VLSI designs. Multiplexer (MUX) is a basic component massively used in typical VLSI designs. In this paper, we focus on the minimization of switching activities in a MUX tree composed of'2-to-1 MUXes. The key contribution of this paper is: Given the on probabilities and the selection probabilities of input data signals, the proposed heuristic algorithm can properly encode all input data signals such that the power consumption of the resultant MUX tree is minimized. For a 64-to-1 MUX, the experimental results show that a MUX tree encoded by the proposed algorithm consumes 24% less power than a randomly-encoded tree on average.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Synchronous Sampling and SNR-Based Gain Control in DS/CDMA Systems DS/CDMA系统中的同步采样和基于信噪比的增益控制
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373229
You-Hsien Lin, Shih-Lin Lo, Wei-Chi Lai, Ta-Yang Juan, Terng-Yin Hsu
{"title":"Synchronous Sampling and SNR-Based Gain Control in DS/CDMA Systems","authors":"You-Hsien Lin, Shih-Lin Lo, Wei-Chi Lai, Ta-Yang Juan, Terng-Yin Hsu","doi":"10.1109/VDAT.2007.373229","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373229","url":null,"abstract":"Timing synchronization is an important component in a receiver designed to recover data form sampling digital waveform. A synchronous sampling recovery with dual correlator differential (DCD) based acquisition with effects of auto-gain controller (AGC) is proposed to achieve fast timing acquisition for direct sequence / code division multiple access (DS/CDMA) system over frequency-selective fading channel in this paper. It measures both received DCD difference power to determine the good sampling phase from an all-digital phase interpolator based multiphase generator. This solution can tolerate + 50ppm system clock offset (SCO) under frequency-selective fading channel. Hence, we not only to determine the good sampling phase fast, but also to arrive stable variable gain amplifier (VGA) with AGC controller in DS/CDMA system approaches.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132732627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microarchitecture-Aware Floorplanning for Processor Performance Optimization 基于微架构的处理器性能优化布局
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373224
Chi-Ying Chen, Juinn-Dar Huang, Hung-Ming Chen
{"title":"Microarchitecture-Aware Floorplanning for Processor Performance Optimization","authors":"Chi-Ying Chen, Juinn-Dar Huang, Hung-Ming Chen","doi":"10.1109/VDAT.2007.373224","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373224","url":null,"abstract":"Previous generation floorplanners had objectives focused on smaller area and wirelength. These objectives were considered sufficient since the latencies of interconnects could be neglected. As technology advances and feature size continues to shrink, the communication of signals on interconnects becomes multi-cycled, hence the latencies can not be ignored. These interconnect latencies have impacts on the performance of the processor, and most of state-of-the-art floorplanning frameworks do not consider these issues. In this paper, we propose a methodology based on a heuristic for better performance in terms of microarchitecture and floorplanning, and it is more efficient than previous works shown in the literature. The experimental results from a subset of MIPS show that our methodology can better the processor performance. The performance has been improved by up to 35.75% when compared to the floorplanning results from conventional objectives, with few extra overhead on area and wirelength. We also found that the intuition of pressing wirelength for floorplan optimization may not get performance edge.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127866629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dynamic Phase-Frequency Recovery for Power Reduction in OFDM Systems 一种用于OFDM系统功率降低的动态相位-频率恢复方法
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373222
Mei-Hui Yang, J. Yu, Juinn-Ting Chen, Chen-Yi Lee
{"title":"A Dynamic Phase-Frequency Recovery for Power Reduction in OFDM Systems","authors":"Mei-Hui Yang, J. Yu, Juinn-Ting Chen, Chen-Yi Lee","doi":"10.1109/VDAT.2007.373222","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373222","url":null,"abstract":"A dynamic phase and frequency recovery (DPR & DFR) is proposed for power reduction and performance improvement. By the DPR, signal sampling rate is reduced from Nyquist rate (or higher) to the symbol rate, resulting in reduced ADC circuit power. By the DFR, data is recovered from less-interfered signals. In the MB-OFDM UWB system, the simulations show that the system improves 2.3 dB SNR and reduce 43.75% ADC power consumption with the proposed techniques.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114390172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Low-Complexity Fractional Delay All-Pass Filter Design for Time-Domain Interpolation 一种用于时域插值的低复杂度分数延迟全通滤波器设计
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373227
To-Ping Wang, T. Chiueh
{"title":"A Low-Complexity Fractional Delay All-Pass Filter Design for Time-Domain Interpolation","authors":"To-Ping Wang, T. Chiueh","doi":"10.1109/VDAT.2007.373227","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373227","url":null,"abstract":"Fractional delay (FD) filter is widely used in digital receiver for time-domain interpolation, such as for compensating sampling clock offset (SCO). Thiran IIR filter is an FD all-pass filter that can retain excellent frequency response. This paper presents an low-complexity implementation of the Thiran filter with application to the sampling clock offset compensation block in digital communication receivers.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding 用于H. 264高级视频编码的基于上下文的自适应二进制算术编码器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373239
Po-Sheng Liu, Jian-Wen Chen, Y. Lin
{"title":"A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding","authors":"Po-Sheng Liu, Jian-Wen Chen, Y. Lin","doi":"10.1109/VDAT.2007.373239","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373239","url":null,"abstract":"We propose a full hardwired context-based adaptive binary arithmetic encoder for H.264/AVC. Our architecture includes a 14-way context pair generator, a 3-stage pipelined circuit for getting neighboring data and a 4-stage pipelined multiple-mode arithmetic encoder. The context pair generator is composed of binarization and context modeling and it can operate with arithmetic encoder concurrently. The arithmetic encoder can process one bin per cycle. Our whole CABAC encoder is able to process 0.67 bins per cycle on the average. Its performance is adequate for 1080 p (HDTV) resolution at 30 fps when running at 60 MHz.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"427 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131769930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Novel Configurable Architecture of ML-Decomposed Binary Arithmetic Encoder for Multimedia Applications 多媒体用ml分解二进制算法编码器的新型可配置结构
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373238
Yu-Jen Chen, Chen-Han Tsai, Liang-Gee Chen
{"title":"Novel Configurable Architecture of ML-Decomposed Binary Arithmetic Encoder for Multimedia Applications","authors":"Yu-Jen Chen, Chen-Han Tsai, Liang-Gee Chen","doi":"10.1109/VDAT.2007.373238","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373238","url":null,"abstract":"A novel architecture of ML-decomposed binary arithmetic coder is proposed. Through the analysis of previous designs, the traditional processing unit is divided into two parts, MPS encoder and LPS encoder. With different arrangements of these two basic components, we develop two types of ML-decomposed structures. To increase the throughput of arithmetic coding, ML cascade architecture puts the coders in serial, while throughput-selection architecture offers several choices in parallel. Their design methodologies are described in this paper. Both methods achieve very high throughput, more than 800 M symbols/sec. And they are configurable and extensible to supply a wide range of specifications. Moreover, the proposed architecture can be used in binary arithmetic coding of various video and image standards.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Low Phase Noise Differential CMOS VCO Based on Tapped-Inductor Resonator 基于抽头电感谐振器的低相位噪声差分CMOS压控振荡器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373249
Yun-Hsueh Chuang, S. Jang, Chien-Feng Lee, Shao-Hua Lee, Cheng-Bing Liu
{"title":"Low Phase Noise Differential CMOS VCO Based on Tapped-Inductor Resonator","authors":"Yun-Hsueh Chuang, S. Jang, Chien-Feng Lee, Shao-Hua Lee, Cheng-Bing Liu","doi":"10.1109/VDAT.2007.373249","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373249","url":null,"abstract":"The design of a low phase noise 4 GHz voltage controlled oscillator (VCO) based on tapped inductor with 10% frequency tuning range fabricated in 0.18-um 1P6M CMOS technology is reported. The LC resonator consists of two tapped inductors and varactors. The varactors have one control terminal to vary the effective resonator capacitance, which is used to fine tune VCO output frequency. The VCO core consumes power of 7.5 mW at 1.5 V supply voltage. The measured phase noise is -121 dBc/Hz at 1MHz offset from the oscillation frequency of 4.4 GHz. The oscillation frequency can be tuned from to 4.05 GHz to 4.47 GHz. This topology can reduce the drain-to-body junction capacitance and can increase the tuning range.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128430466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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