Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance Per Watt Microprocessor

Abstract

As performance per Watt concept being adapted on CPU's performance, a comprehensive post-silicon design methodology on chip power characterization, debug, and validation developed for an energy-efficient product performance become ever more important. An infrared photon-emission (IREM) based technique has been established to meet the needs. With those developed tool capabilities, we can validate simulated fullchip power, determine the causes of excessive power leakage, generate die power and thermal maps, and eventually optimize follow-on designs for power performance. This newly developed techniques have been applied and proven reusable on multiple core microprocessors fabricated under 90 nm and 65 nm CMOS technology. Examples of 5-8% power saving as compared with the first silicon data are presented here to demonstrate the success on debug and design optimization on full chip power.