{"title":"Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H)","authors":"C. Wey, Wei-Chien Tang, Shin-Yo Lin","doi":"10.1109/VDAT.2007.373250","DOIUrl":null,"url":null,"abstract":"An efficient FFT (fast Fourier transform) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This study developed four types of efficient memory-based Radix-2 FFT architecture with a memory size of N words for N-point FFT operations. The latency can be improved from (N/2)+(N/ 2)logN, to (N/2+2)+(N/4)logN, further to [N/2+2]+(N/8) logN, at the cost of increased hardware. Results show that the developed parallel memory-based architecture can achieve a latency of 140 us with 2.425 mm2 in area for N=8192, which is well suitable for being implemented in DVB-T/H.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2007.373250","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
An efficient FFT (fast Fourier transform) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This study developed four types of efficient memory-based Radix-2 FFT architecture with a memory size of N words for N-point FFT operations. The latency can be improved from (N/2)+(N/ 2)logN, to (N/2+2)+(N/4)logN, further to [N/2+2]+(N/8) logN, at the cost of increased hardware. Results show that the developed parallel memory-based architecture can achieve a latency of 140 us with 2.425 mm2 in area for N=8192, which is well suitable for being implemented in DVB-T/H.