A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS

Abstract

This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.