{"title":"在90纳米CMOS 1V 10位400MS/s电流转向D/A转换器","authors":"Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, W. Huang","doi":"10.1109/VDAT.2007.373232","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS\",\"authors\":\"Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, W. Huang\",\"doi\":\"10.1109/VDAT.2007.373232\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.\",\"PeriodicalId\":137915,\"journal\":{\"name\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2007.373232\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2007.373232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
本文介绍了一种90 nm CMOS 1 V 10位400MS/s数模转换器的设计。电流导向架构分为6个MSB一元单元和4个LSB二元加权单元，用于高速运行。给出了大差分满量程输出电压0.5 Vpp的低电压设计。布局后仿真结果表明，在400ms /s的满量程10.15 MHz输入下，SFDR和ENOB分别为64.4 dB和9.36 bit。该芯片工作在1 V的DAC核心电源和2.5 V的I/O接口电源下，采用90纳米CMOS技术制造。其活动面积为0.51 x 0.55 mm2。
A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS
This paper presents the design of a 90 nm CMOS 1 V 10-bit 400MS/s digital-to-analog converter. Current-steering architecture segmented into 6 MSB unary and 4 LSB binary-weighted cells is employed for high-speed operations. The low voltage design with a large differential full-scale output voltage 0.5 Vpp is presented. The post-layout simulation results show that the SFDR and ENOB are 64.4 dB and 9.36 bit respectively with a full-scale 10.15 MHz input at 400 MS/s. This chip operates at a 1 V supply for the DAC core and 2.5 V for I/O interface and is fabricated in a 90 nm CMOS technology. Its active area is 0.51 x 0.55 mm2.
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