A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI:10.1109/VDAT.2007.373220

D. Lin, Chien-Ching Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

引用次数: 7

Abstract

The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.

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基于稀疏状态转换和可变截断长度的低功耗维特比解码器

ACS计算和幸存者内存是最关键的功耗，在Viterbi解码器中消耗约90%的功耗。基于低功耗机制、稀缺状态转换(SST)技术和可变截断长度，提出了一种适用于MB-OFDM超宽带应用的Viterbi解码器。SST方案降低了ACS单元中的状态转换和信号切换。此外，可变截断长度的译码导致幸存者存储器中的访问减少。实验结果表明，在高信噪比下，与不加SST和可变截断长度的情况相比，功率降低了30%以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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