多线程异构MPSoC的混合软硬件多级建模与仿真

K. Popovici, X. Guerin, L. Brisolara, A. Jerraya
{"title":"多线程异构MPSoC的混合软硬件多级建模与仿真","authors":"K. Popovici, X. Guerin, L. Brisolara, A. Jerraya","doi":"10.1109/VDAT.2007.373215","DOIUrl":null,"url":null,"abstract":"In this paper, we introduce a mixed hardware -software architecture model to abstract hardware-software interfaces of multithreaded heterogeneous multiprocessor architecture with specific hardware I/O. We use Simulink environment as modeling language to capture this representation. We generate two intermediate simulation models called Virtual Architecture and Transaction Accurate to validate the software during the different design steps. The software refinement is performed by automatic software code generation for parallel application from Simulink model, and automatic low level software customization for specific architecture. Through experiments we show the efficiency of the proposed design flow that decreases design time without affecting design quality.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Mixed Hardware Software Multilevel Modeling and Simulation for Multithreaded Heterogeneous MPSoC\",\"authors\":\"K. Popovici, X. Guerin, L. Brisolara, A. Jerraya\",\"doi\":\"10.1109/VDAT.2007.373215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we introduce a mixed hardware -software architecture model to abstract hardware-software interfaces of multithreaded heterogeneous multiprocessor architecture with specific hardware I/O. We use Simulink environment as modeling language to capture this representation. We generate two intermediate simulation models called Virtual Architecture and Transaction Accurate to validate the software during the different design steps. The software refinement is performed by automatic software code generation for parallel application from Simulink model, and automatic low level software customization for specific architecture. Through experiments we show the efficiency of the proposed design flow that decreases design time without affecting design quality.\",\"PeriodicalId\":137915,\"journal\":{\"name\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2007.373215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2007.373215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

本文引入了一种软硬件混合体系结构模型,对具有特定硬件I/O的多线程异构多处理器体系结构的软硬件接口进行抽象。我们使用Simulink环境作为建模语言来捕获这种表示。我们生成了虚拟体系结构和事务精确两个中间仿真模型,以在不同的设计阶段对软件进行验证。采用Simulink模型自动生成并行应用的软件代码,以及针对特定体系结构的底层软件自动定制,实现了软件的精细化。通过实验,我们证明了所提出的设计流程在不影响设计质量的情况下减少了设计时间的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Mixed Hardware Software Multilevel Modeling and Simulation for Multithreaded Heterogeneous MPSoC
In this paper, we introduce a mixed hardware -software architecture model to abstract hardware-software interfaces of multithreaded heterogeneous multiprocessor architecture with specific hardware I/O. We use Simulink environment as modeling language to capture this representation. We generate two intermediate simulation models called Virtual Architecture and Transaction Accurate to validate the software during the different design steps. The software refinement is performed by automatic software code generation for parallel application from Simulink model, and automatic low level software customization for specific architecture. Through experiments we show the efficiency of the proposed design flow that decreases design time without affecting design quality.
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