An LLC-OCV Methodology for Statistic Timing Analysis

Abstract

With further increase in chip size and shrink in device dimension, the influence of on chip semiconductor process variation can no longer be ignored in design phase such as STA sign-off. This paper presents the LLC-OCV methodology, which adopts the Monte Carlo analysis to enhance the location-based OCV (LOCV) with gate-level and cell-based perspectives, to be used as a reasonable and complete intra-die process model for STA (statistic timing analysis) sign-off. This new approach shows good prediction for STA sign-off. With LLC-OCV methodology, this paper has correctly identified timing problems in real silicon projects of 0.13 mum process in STA sign-off stage. Comparing the STA results of LOCV and LLC-OCV methodology, our experiment shows that LLC-OCV approach can avoid pessimistic analysis and save chip area.