On-Chip VDC Circuit for SRAM Power Management

Abstract

Leakage current becomes the dominant factor for contributing to the static power consumption. Power management technique is then required to bring down the power consumption. One of the most effective methods is to reduce the power supply voltage in the standby mode or in the power down active mode. In this paper, a simple on-chip voltage down converter is proposed. By designing an internal reference voltage that is proportional to the device threshold voltage, the SRAM cell circuit states can be preserved within a broad range of power supply and temperature. For the 1V-to-0.6V dc-dc conversion, this on-chip VDC only consumes 156 muW standby power and is within 2 mV output voltage variation for load current varying from 1 mu A to 10 mA. By comparing with other power management techniques, the on-chip VDC method is excellent in the static power saving, overall design simplicity and small layout area.