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2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability 考虑热载波可靠性的混合电压I/O缓冲器设计
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373205
M. Ker, Fang-Ling Hu
{"title":"Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability","authors":"M. Ker, Fang-Ling Hu","doi":"10.1109/VDAT.2007.373205","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373205","url":null,"abstract":"A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2timesVDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-mum CMOS process to receive 3.3-V (2timesVDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Analysis and Design of a 1V Charge Sampling Readout Amplifier in 90nm CMOS for Medical Imaging 医学成像用90nm CMOS 1V电荷采样读出放大器的分析与设计
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373212
Linga Reddy Cenkeramaddi, T. Ytterdal
{"title":"Analysis and Design of a 1V Charge Sampling Readout Amplifier in 90nm CMOS for Medical Imaging","authors":"Linga Reddy Cenkeramaddi, T. Ytterdal","doi":"10.1109/VDAT.2007.373212","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373212","url":null,"abstract":"In this paper, we present the analysis and design of a charge sampling amplifier (CSA) in 90 nm CMOS for medical imaging applications. The CSA is designed based on a 1 V CMOS folded cascode operational transconductance amplifier (OTA) with lead compensation. The OTA achieves a DC gain of 45-dB and a unity gain frequency of 1.3 GHz at a power consumption of 200 muW. Performance of the charge sampling amplifier is investigated when it is connected to a single capacitive micro machined ultrasound transducer (CMUT). The proposed CSA front end architecture for ultrasound imaging achieves a transfer gain of 19 dB from CMUT signal source to the output of the CSA (across feedback capacitor) with sampling simultaneously.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Stable Performance MAC Protocol for HOY Wireless Tester under Large Population 大人口下HOY无线测试仪性能稳定的MAC协议
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373235
Te-Wen Ko, Yu-Tsao Hsing, Cheng-Wen Wu, Chih-Tsun Huang
{"title":"Stable Performance MAC Protocol for HOY Wireless Tester under Large Population","authors":"Te-Wen Ko, Yu-Tsao Hsing, Cheng-Wen Wu, Chih-Tsun Huang","doi":"10.1109/VDAT.2007.373235","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373235","url":null,"abstract":"It has been widely noted that the traditional test equipments cannot catch up with the increasing speed, pin count, and parameter accuracy of advanced IC products, rapidly increasing the test cost for semiconductor chips and wafers. To solve this problem, we had proposed a novel wireless test system called HOY. In this paper we present a stable performance MAC Protocol for the HOY wireless tester under large population. It provides three functions: Test Initialization (TI), NACK Based Reliable Multicast (NBRM), and Polling. The tester may use TI to gather information from the dies under tests (DUTs) and apply NBRM to transmit test commands to the DUTs. Upon finishing the test process, the HOY tester collects the test results by Polling. The stable performance indices include the throughput and average performance TI, and the reliability and transmission time of NBRM. We show that the number of DUTs has little effect on performance, making the improvement of test parallelism promising for the HOY approach.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133619706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Minimizing Energy Consumption with Variable Forward Body Bias for Ultra-Low Energy LSIs 超低能量lsi的可变前倾最小化能耗
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373206
S. Jayapal, Y. Manoli
{"title":"Minimizing Energy Consumption with Variable Forward Body Bias for Ultra-Low Energy LSIs","authors":"S. Jayapal, Y. Manoli","doi":"10.1109/VDAT.2007.373206","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373206","url":null,"abstract":"Ultra-low energy LSI becomes primary concern in today's battery driven ubiquitous computing portable applications. To reduce energy per transition and to enhance performance in the ultra-low voltage region, we review the variable forward body bias scheme to make either faster pull-up or pull-down transition in the sub-threshold, near-threshold and above-threshold regimes. We begin our study for minimizing energy per transition by applying variable forward body bias asymmetrically and propose novel approaches to energy efficient design with performance advantages. To analyze and discuss, the fan-out of 3 (FO3) inverter based 51-stage delay chain is simulated in an industrial 130 nm triple well process technology.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 256×128 Energy-Efficient TCAM with Novel Low Power Schemes 一种新颖低功耗方案的256×128节能TCAM
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373204
Po-Tsang Huang, Shu‐Wei Chang, Wen-Yen Liu, W. Hwang
{"title":"A 256×128 Energy-Efficient TCAM with Novel Low Power Schemes","authors":"Po-Tsang Huang, Shu‐Wei Chang, Wen-Yen Liu, W. Hwang","doi":"10.1109/VDAT.2007.373204","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373204","url":null,"abstract":"Novel low power schemes for energy-efficient ternary content-addressable memory (TCAM) are presented in this paper. The butterfly match-line scheme is based on the pseudo-footless clock-data pre-charged architecture. It connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. For applications like IP-address forwarding in a network router, a new don't-care based power gating and don't-care based hierarchical (DCBH) search-line scheme are proposed. The search-line is divided into global search-line (GSL) and local search-line (LSL) which is controlled by don't-care state in DCBH search-line scheme. Therefore, the power consumption on search line is reduced without any search time overhead. Besides, the power saving of the standby power is achieved by power gating technique. The proposed 256 times 128 bit TCAM has been implemented with TSMC 0.13 um CMOS technology. It shows 0.55 ns of match evaluation time on search operation with 0.29 fJ/bit/search of energy efficiency.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131583160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Joint Architecture of Error-Concealed Deblocking Filter for H.264/AVC Video Transmission 一种用于H.264/AVC视频传输的隐错块滤波器联合结构
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373240
Wen-Ping Lee, Tsu-Ming Liu, Chen-Yi Lee
{"title":"A Joint Architecture of Error-Concealed Deblocking Filter for H.264/AVC Video Transmission","authors":"Wen-Ping Lee, Tsu-Ming Liu, Chen-Yi Lee","doi":"10.1109/VDAT.2007.373240","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373240","url":null,"abstract":"In this paper, we propose new spatial error concealment (SEC) method, error-concealed de-blocking filter (ECDF), for a real-time decoding system over an error-prone or wireless channel. There are several advantages of ECDF. The first is that ECDF can conceal I frames without the need of flexible macroblock ordering (FMO). Second, the hardware cost of interpolation can be saved. Third, the required information for error concealment (EC) only includes the pixels in the top and left neighbors of current corrupted macroblock (MB). Hence, we can conceal the corrupted MB without requiring the information in the right and bottom side, leading to the reduction of memory space as well as bandwidth. The implementation results show that the hardware cost of ECDF can be saved about 30% compared to direct implementation. Without the FMO, the proposal gains 1.3dB in PSNR compared to bilinear interpolation in JM9.8.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123593827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Switch Controlled Source Amplifier for Low Power Mobile TFT-LCD Driver IC 用于低功率移动TFT-LCD驱动IC的开关控制源放大器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.372758
J. Woo, J.G. Lee, K. Y. Chung, W. Kang, S.C. Kim, G. Lee, I. Kang, B.N. Kim
{"title":"Switch Controlled Source Amplifier for Low Power Mobile TFT-LCD Driver IC","authors":"J. Woo, J.G. Lee, K. Y. Chung, W. Kang, S.C. Kim, G. Lee, I. Kang, B.N. Kim","doi":"10.1109/VDAT.2007.372758","DOIUrl":"https://doi.org/10.1109/VDAT.2007.372758","url":null,"abstract":"Switch controlled source amplifier (SCSA) is proposed for low power mobile TFT-LCD driver ICs (T-LDIs). In SCSA scheme, the operation of the source drivers in a T-LDI is determined by the source line load of TFT-LCD. That is, output stage current of source buffers is reduced when the source line load is separated for current saving operation such as charge sharing between VCOM and source lines. With SCSA scheme, all the static current of source buffers can be reduced as far as phase margin of the output buffers is permitted. A test chip was fabricated in a 5-V/0.8-mum triple-metal CMOS process with QVGA resolution, and the experimental results show that the power consumption of 11%~16% was saved with die size overhead less than 1%.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115819324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4-Channel Poly-Phase Filter for Cognitive Radio Systems 用于认知无线电系统的4通道多相滤波器
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373211
Guan-Jun Chen, H. Chiu, Tai-Cheng Lee
{"title":"A 4-Channel Poly-Phase Filter for Cognitive Radio Systems","authors":"Guan-Jun Chen, H. Chiu, Tai-Cheng Lee","doi":"10.1109/VDAT.2007.373211","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373211","url":null,"abstract":"A 4-channel poly-phase filter is proposed for cognitive radio systems. The cognitive radio system can sense the spectrum utilization and achieve higher transmission efficiency. To maximize the dynamic range of the receiver, the multi-channel poly-phase filter is required in the cognitive radio receiver to suppress the interference that is typically generated by legacy users. The filter is able to select different channels according to the demand of the system. A chip is fabricated in 0.18-mum CMOS technology. It dissipates 13.4 mW and achieves 35-dB adjacent channel rejection.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122731190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Microprocessor Modeling and Simulation with SystemC 基于SystemC的微处理器建模与仿真
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373197
Yen-Ju Lu, Chen-Tung Lin, Chi-Feng Wu, Shih-Arn Hwang, Ying-Hsi Lin
{"title":"Microprocessor Modeling and Simulation with SystemC","authors":"Yen-Ju Lu, Chen-Tung Lin, Chi-Feng Wu, Shih-Arn Hwang, Ying-Hsi Lin","doi":"10.1109/VDAT.2007.373197","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373197","url":null,"abstract":"Complexity of advanced chip designs is driving the progress of ESL methodology. SystemC, with its mature C++ language environment and the availability of public tools, is quickly becoming the de facto ESL language. In this paper, we demonstrate the methodology by microprocessor modeling with systemC. Various abstraction levels and the corresponding purposes are addressed. The advantage of ESL methodology is shown by the experimental results of simulation speed. With a 18 times to over 500 times simulation speed-up, the methodology has proved useful in modeling, verification, and software development.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"6 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130099026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1V 5-Bit 5GSample/sec CMOS ADC for UWB Receivers 用于UWB接收器的1V 5位5GSample/sec CMOS ADC
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI: 10.1109/VDAT.2007.373230
I-Hsin Wang, Shen-Iuan Liu
{"title":"A 1V 5-Bit 5GSample/sec CMOS ADC for UWB Receivers","authors":"I-Hsin Wang, Shen-Iuan Liu","doi":"10.1109/VDAT.2007.373230","DOIUrl":"https://doi.org/10.1109/VDAT.2007.373230","url":null,"abstract":"This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistors sizes for the cascaded stages are inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for measurements. This chip has been fabricated in 0.13-mum 1P8M CMOS process and the total power consumption is 113 mW with IV supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200 MHz at 5-GSample/sec.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131747101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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