Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability

Abstract

A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2timesVDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-mum CMOS process to receive 3.3-V (2timesVDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0.