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引用次数: 3
摘要
提出了一种结合模拟自校准电路的延时锁相环(DLL)。当与校准电路和可变延迟输出缓冲器结合使用时,所提出的DLL可以在过程拐角、电压/温度变化和器件不匹配时生成精确的多相时钟。在标准0.35 μ m CMOS工艺中的实验电路表明,在100 MHz下,相位之间的延迟不匹配可以从数十皮秒减少到小于10皮秒。原型电路的面积为2.1 mm2,在3.3 V时消耗约10.1 mW。
A Self-Calibrated Multiphase DLL-Based Clock Generator
A delay-locked loop (DLL) Integrated with an analog self-calibration circuit is presented. The proposed DLL can generate precise multiphase clocks over process corners, voltage/temperature variations and device mismatches when incorporating with the calibration circuit and variable-delay output buffers. The experimental circuit in a standard 0.35-mum CMOS process demonstrates delay mismatch between phases can be reduced from tens of pico-second to less than ten pico-seconds at 100 MHz. The prototype circuit occupies an area of 2.1 mm2, and consumes around 10.1 mW at 3.3 V.