A Low-Power Low-Swing Single-Ended Multi-Port SRAM

Abstract

In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A low-swing 3-port 64times32-bit SRAM macro is simulated in TSMC 130 nm CMOS technology. It consumes a minimum of 725 muW and 658 muW per-port at 1 GHz with 1.2 V supply voltage for read and write power, respectively.