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A physical compact MOSFET model, including quantum mechanical effects, for statistical circuit design applications 一个物理紧凑的MOSFET模型，包括量子力学效应，用于统计电路设计应用
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499370
R. Rios, N. Arora, Chengxiong Huang, N. Khalil, J. Faricelli, L. Gruber
{"title":"A physical compact MOSFET model, including quantum mechanical effects, for statistical circuit design applications","authors":"R. Rios, N. Arora, Chengxiong Huang, N. Khalil, J. Faricelli, L. Gruber","doi":"10.1109/IEDM.1995.499370","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499370","url":null,"abstract":"We present a physical and continuous compact MOSFET model applicable to deep sub-micron devices with very thin gate oxide thicknesses. We focus on the premise that a good compact model should be based on a physical long-channel model that accurately fits both I-V and C-V data. To meet this requirement, we found that the model must account for the correct bias dependency of the surface potential, and include polysilicon depletion and quantum mechanical effects. The resulting model is predictive within a range of the fundamental process parameters, and is thus suitable for statistical circuit simulations.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127848847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
New Monte Carlo simulation for polycrystalline silicon thin-film transistor 多晶硅薄膜晶体管的蒙特卡罗模拟新方法
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499200
T. Shimatani, M. Koyanagi
{"title":"New Monte Carlo simulation for polycrystalline silicon thin-film transistor","authors":"T. Shimatani, M. Koyanagi","doi":"10.1109/IEDM.1995.499200","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499200","url":null,"abstract":"The conduction mechanism in poly-Si TFT is investigated in detail using a new device simulator based on the Monte Carlo method. In this simulator, the influences of grain boundaries on the electrical conduction are represented by the grain boundary traps. The potential barriers are formed at the grain boundaries by the trapped electrons. The conduction electrons are repelled by these potential barriers and the current flow decreases. It is found from the simulation results that these potential barriers are reduced more significantly near the poly-Si-gate oxide interface and consequently the current flow is confined near the interface when a high gate voltage is applied. It also turns out that holes generated by the impact ionization significantly influence the channel electron conduction through reducing the barrier height at the grain boundary. This effect is the origin of the avalanche induced short channel effect in poly-Si TFT.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126635975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Circuit sensitivity analysis in terms of process parameters 根据工艺参数进行电路灵敏度分析
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499371
M. van Dort, D. Klaassen
{"title":"Circuit sensitivity analysis in terms of process parameters","authors":"M. van Dort, D. Klaassen","doi":"10.1109/IEDM.1995.499371","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499371","url":null,"abstract":"A new methodology for sensitivity analysis at circuit level in terms of process parameters is presented. Response functions for long-channel MOSFETs are found from process and device simulations. Responses for a device with arbitrary dimensions are subsequently calculated using the MOS MODEL 9 scaling rules.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126465934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Hot carrier effects in short MOSFETs at low applied voltages 短mosfet在低外加电压下的热载子效应
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499201
A. Abramo, C. Fiegna, F. Venturi
{"title":"Hot carrier effects in short MOSFETs at low applied voltages","authors":"A. Abramo, C. Fiegna, F. Venturi","doi":"10.1109/IEDM.1995.499201","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499201","url":null,"abstract":"In this paper a quantitative study of the electron energy distribution in silicon devices at low applied voltages is carried out by means of Monte Carlo simulations including the main mechanisms involved in the process of carrier heating. We present a clear-cut interpretation of the build up of the electron distribution at energies higher than that provided by the applied electric field (qV, V being the total voltage drop). Electron-electron interaction is analyzed and shown to be an effective process for the enhancement of the high-energy electron population.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122227728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Controlling the device field edge to achieve a low power TFSOI technology 控制器件场边，实现低功耗TFSOI技术
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499358
M. Racanelli, W.M. Huang, H. Shin, J. Foerstner, B. Hwang, S. Cheng, P. Fejes, H. Park, T. Wetteroth, S. Hong, H. Shin, S. Wilson
{"title":"Controlling the device field edge to achieve a low power TFSOI technology","authors":"M. Racanelli, W.M. Huang, H. Shin, J. Foerstner, B. Hwang, S. Cheng, P. Fejes, H. Park, T. Wetteroth, S. Hong, H. Shin, S. Wilson","doi":"10.1109/IEDM.1995.499358","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499358","url":null,"abstract":"The impact of stress and dopant redistribution along the field edge of SOI devices on offstate leakage, low voltage performance, and yield is discussed. For the first time, stress caused by overoxidation of the field region is shown to cause excessive device leakage and yield loss. A modified PBL isolation scheme is used to minimize this effect. Dopant redistribution is known to cause field edge leakage and is shown to contribute to narrow channel effects. A novel integration scheme is described to reduce the impact of dopant redistribution and result in a TFSOI technology suitable for low power applications.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126818477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
EEPROM/flash sub 3.0 V drain-source bias hot carrier writing EEPROM/flash sub 3.0 V漏源偏置热载流子写入
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499382
J. Bude, A. Frommer, M. Pinto, G. Weber
{"title":"EEPROM/flash sub 3.0 V drain-source bias hot carrier writing","authors":"J. Bude, A. Frommer, M. Pinto, G. Weber","doi":"10.1109/IEDM.1995.499382","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499382","url":null,"abstract":"Stacked-gate memory devices have been realized which for the first time demonstrate efficient hot carrier writing for drain-source bias, V/sub DS/, down to 2.5 V. Writing is achieved by channel initiated secondary electron injection, which permits writing for qV/sub DS/ below the 3.2 eV oxide barrier. Writing times of 1 ms are achieved for floating gate voltages V/sub FG/ as low as 1.2 V, with V/sub DS/=-V/sub BS/=2.5 V, voltages which can easily be derived from a single scaled power supply, the back-gate bias generated by low-current charge pumping. No high voltage transistors are required for writing or V/sub T/ convergence. Moreover, because the devices are based on a fully scaled 0.25 /spl mu/m CMOS process, NV-memory arrays can be easily integrated with a minimum of additional process steps. Tight V/sub T/ convergence together with low voltage operation and scaling compatibility makes them ideal candidates for Giga-bit Flash.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121069926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Monolithic planar RF inductor and waveguide structures on silicon with performance comparable to those in GaAs MMIC 单片平面射频电感和波导结构，性能可与GaAs MMIC相媲美
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499319
Bonkee Kim, B. Ko, K. Lee, Ji-Won Jeong, Kun-Sang Lee, Seong-Chan Kim
{"title":"Monolithic planar RF inductor and waveguide structures on silicon with performance comparable to those in GaAs MMIC","authors":"Bonkee Kim, B. Ko, K. Lee, Ji-Won Jeong, Kun-Sang Lee, Seong-Chan Kim","doi":"10.1109/IEDM.1995.499319","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499319","url":null,"abstract":"The monolithic inductors and transmission lines on Si substrate with very high Q factor, low insertion loss, and high resonant frequency, are achieved by using very thick polyimide (10 /spl mu/m) as dielectric material, and thick Al (4 /spl mu/m) metalization system. This structure is made on the finished conventional standard two layer metalization BiCMOS wafer. For 10 nH inductor, 6 GHz resonant frequency, maximum Q factor of 5.5 at 1.2 GHz, and 1.2 dB insertion loss at 3 GHz are obtained, which are very comparable to those available in GaAs MMIC, These inductors can be used as RF choke as well as matching element. Transmission lines are also fabricated using this technology. The S/sub 21/ of coplanar waveguide with 1 mm length is -0.2 dB at 4 GHz, and that of microstrip line is -0.3 dB. It is expected that, using these passive elements, Si RF IC can be designed up to several GHz with performance comparable to GaAs MMIC.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"12 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113962937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
Novel components for wavelength division multiplexed systems based on monolithic multiplexer/amplifier integration 基于单片复用/放大器集成的新型波分复用系统元件
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499283
M. Zirngibl
{"title":"Novel components for wavelength division multiplexed systems based on monolithic multiplexer/amplifier integration","authors":"M. Zirngibl","doi":"10.1109/IEDM.1995.499283","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499283","url":null,"abstract":"We report on monolithically integrated lasers and receivers that are capable of simultaneously sending and receiving signals on several optical wavelengths. The integration scheme on InP assures a very stable optical channel spacing. An application of these components for a broadband fiber-to-the-home network is discussed.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125296899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The numerical simulation of substrate and gate currents in MOS and EPROMs MOS和eprom中衬底和栅极电流的数值模拟
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499198
A. Concannon, F. Piccinini, A. Mathewson, C. Lombardi
{"title":"The numerical simulation of substrate and gate currents in MOS and EPROMs","authors":"A. Concannon, F. Piccinini, A. Mathewson, C. Lombardi","doi":"10.1109/IEDM.1995.499198","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499198","url":null,"abstract":"The gate current that flows during programming in the flash EEPROM device is a result of hot electron injection from the channel. The channel doping is high and the drain junction is abrupt and optimised to enhance the hot carrier avalanche generation in the silicon near the drain junction. As in the case with conventional MOS, this has the further impact of creating a high substrate current. In this work, a new model for both substrate and gate current using the same hot carrier energy distribution function in both models is presented. These models predict gate and substrate currents over a wide range of gate voltages and have been validated for both electron and hole hot carrier avalanche generation in n- and p-channel transistors. These models have been used to simulate flash EEPROM programming so that reliability issues, particularly with respect to the effect of the gate current due to hot hole injection, could be investigated.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125316728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Three dimensional PVD virtual reactor for VLSI metallization 用于VLSI金属化的三维PVD虚拟反应器
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497191
D. Bang, J. Mcvittie, K. Saraswat, Z. Krivokapic, J. Iacoponi, J. Gray
{"title":"Three dimensional PVD virtual reactor for VLSI metallization","authors":"D. Bang, J. Mcvittie, K. Saraswat, Z. Krivokapic, J. Iacoponi, J. Gray","doi":"10.1109/IEDM.1995.497191","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497191","url":null,"abstract":"A three dimensional Physical Vapor Deposition (PVD) virtual reactor is presented which uses 3-d particle flux data generated by equipment level models in order to simulate 3-d metal film profiles for VLSI scale features. A calibration methodology which links the 3-d virtual reactor with a computationally efficient \"3-2d\" simulator is demonstrated, and an accuracy criteria which specifies when the full 3-d code is more accurate than its 3-2d counterpart is calculated. Experimental Ti/Al depositions were performed for 3-d structures, and the corresponding SEM cross sections are compared to simulated data.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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