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Proceedings of International Electron Devices Meeting最新文献

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On-state reliability of amorphous silicon antifuses 非晶硅防熔丝的导通可靠性
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499281
G. Zhang, Y. King, S. Elfoukhy, E. Hamdy, T. Jing, P. Yu, C. Hu
{"title":"On-state reliability of amorphous silicon antifuses","authors":"G. Zhang, Y. King, S. Elfoukhy, E. Hamdy, T. Jing, P. Yu, C. Hu","doi":"10.1109/IEDM.1995.499281","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499281","url":null,"abstract":"A unified model of the on-state reliability of a-Si antifuses is presented. This physical model accounts for both thermal activation and electromigration. Temperature at the conductive link is the temperature at which the antifuse is stressed and is controlled by the stress current, not the ambient. To ensure a 10 year lifetime, a-Si antifuses should be operated at a current value less than 60% of its programming current value.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125083703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes 深亚微米CMOS工艺中衬底触发和盐化物对ESD性能的影响及保护电路设计
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499280
A. Amerasekera, C. Duvvury, Vijay Reddy, Mark S. Rodder
{"title":"Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes","authors":"A. Amerasekera, C. Duvvury, Vijay Reddy, Mark S. Rodder","doi":"10.1109/IEDM.1995.499280","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499280","url":null,"abstract":"The effect of salicides and the influence of the local substrate potential on ESD performance of deep submicron nMOS transistors have been studied. It is shown that salicidation causes a strong dependence of ESD performance on effective channel length in these devices. Salicides also impact the behavior of the lateral npn parasitic bipolar transistor by affecting the emitter efficiency. A higher local substrate potential has been shown to have a positive impact on ESD performance. Based on these results we have designed and demonstrated a substrate triggered nMOS protection circuit which provides >2 kV ESD performance in a fully salicided process.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128342174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 92
1.2 V operation 1.1 W heterojunction FET for portable radio applications 用于便携式无线电应用的1.2 V操作1.1 W异质结FET
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.497210
K. Inosako, N. Iwata, M. Kuzuhara
{"title":"1.2 V operation 1.1 W heterojunction FET for portable radio applications","authors":"K. Inosako, N. Iwata, M. Kuzuhara","doi":"10.1109/IEDM.1995.497210","DOIUrl":"https://doi.org/10.1109/IEDM.1995.497210","url":null,"abstract":"This paper describes 1.2 V operated power performance of a double-doped AlGaAs-InGaAs-AlGaAs heterojunction FET (HJFET) at 950 MHz. A 28 mm gate periphery HJFET delivered a saturated output power of 1.1 W for maximum output power tuning and a maximum power-added efficiency of 63% for maximum efficiency tuning. These results significantly advance the state-of-the-art of low voltage operation power devices for portable radio applications.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128508434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Dynamic aging of CMOS SOI transistors in circuit operation CMOS SOI晶体管在电路运行中的动态老化
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499303
E. Guichard, G. Reimbold, S. Cristoloveanu, C. Leroux, D. Blachier, G. Borel, B. Giffard
{"title":"Dynamic aging of CMOS SOI transistors in circuit operation","authors":"E. Guichard, G. Reimbold, S. Cristoloveanu, C. Leroux, D. Blachier, G. Borel, B. Giffard","doi":"10.1109/IEDM.1995.499303","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499303","url":null,"abstract":"SOI transistors, operating in dynamic mode, have been fully investigated using dedicated test circuits. Indeed, specific circuits have been built in order to make, in-situ monitoring of electrical characteristics of n- and p-MOSFETs. We have demonstrated that physical mechanisms of the degradation, in partially depleted SOI devices, are comparable after static and dynamic stress. Indeed, back interface degradation analysis has revealed that, even after dynamic aging, p-MOSFETs are submitted to electron trapping while it is not the case for n-MOSFETs. The \"quasi static\" approach is not applicable in inverter-type circuit, and could be explained by successive injection of holes and electrons due to the specific bias waveform, leading to an enhancement of the degradation.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128210743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Excellent electro/stress-migration-resistance surface-silicide passivated giant-grain Cu-Mg alloy interconnect technology for giga scale integration (GSI) 优异的抗电/应力迁移表面硅化钝化大晶粒铜镁合金互连技术
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499190
T. Takewaki, R. Kaihara, T. Ohmi, T. Nitta
{"title":"Excellent electro/stress-migration-resistance surface-silicide passivated giant-grain Cu-Mg alloy interconnect technology for giga scale integration (GSI)","authors":"T. Takewaki, R. Kaihara, T. Ohmi, T. Nitta","doi":"10.1109/IEDM.1995.499190","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499190","url":null,"abstract":"Completely (100)-oriented Cu-Mg films having giant grains (typical grain sizes of /spl sim/100 /spl mu/m) were obtained by depositing Cu-Mg films on SiO/sub 2/ followed by thermal annealing at 450/spl deg/C. The Cu-Mg film exhibits a room temperature resistivity of 1.81 /spl mu//spl Omega//spl middot/cm. And this interconnect exhibits 3 times larger migration resistance than the giant-grain Cu interconnect. Furthermore, by employing the self-aligned surface-silicide passivation to the Cu-Mg interconnect, the migration resistance is greatly enhanced. It exhibits two orders of magnitude larger migration resistance than non-passivated giant-grain Cu interconnect at a room temperature.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128232934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROMs 一种用于多级NAND eeprom的新型侧壁转移晶体管电池(SWATT电池)
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499195
S. Aritome, Y. Takeuchi, S. Sato, H. Watanabe, K. Shimizu, G. Hemink, R. Shirota
{"title":"A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROMs","authors":"S. Aritome, Y. Takeuchi, S. Sato, H. Watanabe, K. Shimizu, G. Hemink, R. Shirota","doi":"10.1109/IEDM.1995.499195","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499195","url":null,"abstract":"A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (Vth) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide Vth is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the Vth of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the Vth distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell realizes a very small cell size of 0.67 /spl mu/m/sup 2/ for a 0.35 /spl mu/m rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROMs of 512 Mbit and beyond.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129968462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Model for degradation of GaAs/AlGaAs HBTs under temperature and current stress 温度和电流应力下GaAs/AlGaAs HBTs的降解模型
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499341
T. Henderson
{"title":"Model for degradation of GaAs/AlGaAs HBTs under temperature and current stress","authors":"T. Henderson","doi":"10.1109/IEDM.1995.499341","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499341","url":null,"abstract":"The similarities between GaAs/AlGaAs heterojunction bipolar transistors (HBTs) and GaAs-based light-emitting diodes (LEDs) and laser diodes (LDs) under current and temperature stress are demonstrated. Electroluminescence on HBTs with degraded current gain shows a marked decrease in light emission. One device which suffered rapid degradation in current gain also showed a <110> dark line defect (DLD). Finally, an equation used to model light output as a function of time under bias stress in LEDs and LDs was modified to model collector current vs. time for HBTs under bias stress. An excellent fit to the data is shown.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130147863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Simulation and modeling of the effect of substrate conductivity on coupling inductance 衬底电导率对耦合电感影响的仿真与建模
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499245
Y. Massoud, J. White
{"title":"Simulation and modeling of the effect of substrate conductivity on coupling inductance","authors":"Y. Massoud, J. White","doi":"10.1109/IEDM.1995.499245","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499245","url":null,"abstract":"The goal of this work was to extend the FASTHENRY 3-D inductance extraction program to include the finite conductivity of a semiconductor substrate, and then use the modified program to investigate a variety of on-chip inductive effects. In addition, the limitations of a simple two-loop model for estimating coupling inductance is examined.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131059802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A scalable low power vertical memory 可扩展的低功耗垂直存储器
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499305
H. Hanafi, S. Tiwari, S. Burns, W. Kocon, A. Thomas, N. Garg, K. Matsushita
{"title":"A scalable low power vertical memory","authors":"H. Hanafi, S. Tiwari, S. Burns, W. Kocon, A. Thomas, N. Garg, K. Matsushita","doi":"10.1109/IEDM.1995.499305","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499305","url":null,"abstract":"An experimental memory array with the capability of operation at cell area below 0.15 /spl mu/m/sup 2/ for the gigabit generation is described. Channel injection through a thin oxide (/spl sime/3 nm) into the floating gate of a vertical transistor allow scalable, ultra-low power, and dense (4-6 square of the minimum pitch) structures that operate with 100 ns write speeds at low voltages, >10/sup 5/ s retention time, and endurance exceeding 10/sup 10/ cycles with no measurable degradation. Non-volatile structures are achieved with a compromise in speed and power. Multiple-self alignment and use of thin film growth, deposition, and etching techniques allow for a significant reduction in the lithography needs.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130519256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Embedded micromechanical devices for the monolithic integration of MEMS with CMOS 用于MEMS与CMOS单片集成的嵌入式微机械器件
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499295
J.H. Smith, S. Montague, J. Sniegowski, J. Murray, P. McWhorter
{"title":"Embedded micromechanical devices for the monolithic integration of MEMS with CMOS","authors":"J.H. Smith, S. Montague, J. Sniegowski, J. Murray, P. McWhorter","doi":"10.1109/IEDM.1995.499295","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499295","url":null,"abstract":"A flexible, modular manufacturing process for integrating micromechanical and microelectronic devices has been developed. This process embeds the micromechanical devices in an anisotropically etched trench below the surface of the wafer. Prior to microelectronic device fabrication, this trench is refilled with oxide, chemical-mechanically polished, and sealed with a nitride cap in order to embed the micromechanical devices below the surface of the planarized wafer. The feasibility of this technique in a manufacturing environment has been demonstrated by combining a variety of embedded micromechanical structures with a 2 /spl mu/m CMOS process on 6 inch wafers. A yield of 78% has been achieved on the first devices manufactured using this technique.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 211
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