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Proceedings of International Electron Devices Meeting最新文献

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Extended study of crosstalk in SOI-SIMOX substrates SOI-SIMOX衬底串扰的扩展研究
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499318
A. Viviani, J. Raskin, D. Flandre, J. Colinge, D. Vanhoenacker
{"title":"Extended study of crosstalk in SOI-SIMOX substrates","authors":"A. Viviani, J. Raskin, D. Flandre, J. Colinge, D. Vanhoenacker","doi":"10.1109/IEDM.1995.499318","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499318","url":null,"abstract":"This work analyzes crosstalk phenomena in SOI-SIMOX substrates by means of two-dimensional device simulations and measurements on test structures. The influence of the substrate resistivity and of guard rings is studied. The results are compared with those obtained for standard CMOS technology. A significant crosstalk reduction, up to 10 GHz, is obtained with high-resistivity substrates. A simple modeling is proposed to explain and simulate the phenomenon.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"9 20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127903740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Efficient non-quasi-static MOSFETs model for circuit simulation 高效非准静态mosfet电路仿真模型
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499372
E. Dubois, E. Robilliart
{"title":"Efficient non-quasi-static MOSFETs model for circuit simulation","authors":"E. Dubois, E. Robilliart","doi":"10.1109/IEDM.1995.499372","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499372","url":null,"abstract":"A fast numerical resolution of the Poisson and current continuity equations is used to model non-quasi-static effects in MOS circuits under fast switching conditions. The resulting model is continuous over all regimes of operation and accounts for the non-instantaneous redistribution of the channel charge. The capabilities of this modelling approach are exemplified through the simulation of current mode analog circuits.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121616742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Si/SiGe high-speed field-effect transistors Si/SiGe高速场效应晶体管
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499249
K. Ismail
{"title":"Si/SiGe high-speed field-effect transistors","authors":"K. Ismail","doi":"10.1109/IEDM.1995.499249","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499249","url":null,"abstract":"We review the current status of Si/SiGe n- and p-type MODFETs with an emphasis on their microwave performance. A comparison with state-of-the-art Si technology is given, and the potential use of Si/SiGe devices in complementary logic is pointed out.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Si/Ge/sub x/Si/sub 1-x/ HBTs with the Ge/sub x/Si/sub 1-x/ base formed by high dose Ge implantation in Si Si/Ge/sub -x/ Si/sub - 1-x/ HBTs与高剂量Ge注入Si形成的Ge/sub -x/ Si/sub - 1-x基
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499390
S. Lombardo, A. Pinto, V. Raineri, P. Ward, S. U. Campisano
{"title":"Si/Ge/sub x/Si/sub 1-x/ HBTs with the Ge/sub x/Si/sub 1-x/ base formed by high dose Ge implantation in Si","authors":"S. Lombardo, A. Pinto, V. Raineri, P. Ward, S. U. Campisano","doi":"10.1109/IEDM.1995.499390","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499390","url":null,"abstract":"We have fabricated n-p-n Si/Ge/sub x/Si/sub 1-x/ heterojunction bipolar transistors with the Ge/sub x/Si/sub 1-x/ base formed by high dose Ge implantation followed by rapid thermal annealing at 1000/spl deg/C for 10 s. The fabrication technology is a standard self-aligned, double polysilicon process scheme for Si with the addition of the high dose Ge implantation. The transistors are characterized by a 60 nm wide neutral base with a Ge concentration peak of /spl ap/7 at.% at the base-collector junction. For the first time using this fabrication technology, good static electrical characteristics are demonstrated. Compared to Si homojunction transistors with similar values of current gain and Early voltage, the Ge/sub x/Si/sub 1-x/ devices show base resistances more than two times lower.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"37 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131589720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS process design for minimization of IC power consumption using TCAD 利用TCAD设计CMOS工艺，使IC功耗最小化
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499242
A. von Schwerin, D. Schumann, J. Berthold
{"title":"CMOS process design for minimization of IC power consumption using TCAD","authors":"A. von Schwerin, D. Schumann, J. Berthold","doi":"10.1109/IEDM.1995.499242","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499242","url":null,"abstract":"CMOS low-voltage process design is presented as an example of industrial application of technology CAD. TCAD tools are used to evaluate G/sub P/, the gain in power efficiency (i.e. battery lifetime) which is achievable by reduction of supply voltage (V/sub dd/) with adaptation of threshold voltage (V/sub th/) and gate length scaling for constant performance. The trade-off between leakage and active power depending on the IC properties is studied. Maximum G/sub P/ found for a 16 bit microprocessor with 32 kB on chip SRAM is about 7 for V/sub th/ of /spl plusmn/0.3V and V/sub dd/ of 1.3V.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132685432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's 高f/sub T/和f/sub max/硅双极晶体管，采用超高性能超自对准工艺技术，用于低能耗和超高速LSI
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499323
M. Ugajin, J. Kodate, Y. Kobayashi, S. Konaka, T. Sakai
{"title":"Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's","authors":"M. Ugajin, J. Kodate, Y. Kobayashi, S. Konaka, T. Sakai","doi":"10.1109/IEDM.1995.499323","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499323","url":null,"abstract":"Very-high f/sub T/ (up to 50 GHz) and f/sub max/ (up to 70 GHz) silicon bipolar transistors have been developed using Ultra-high-performance Super Self-aligned process Technology (USST). This technology is characterized by drastically-scaled lateral dimensions and shallow, heavily-doped extrinsic base structures. USST greatly reduces base-collector junction capacitance and base resistance, and hence makes f/sub max/ about twice as large as SST1C technology without vertical scaling. The fabricated ECL circuits show a minimum gate delay of 16.5 ps at a switching current of I/sub CS/=1.0 mA/G.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"55 25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128846916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Modeling the effects of traps on the I-V characteristics of GaAs MESFETs 陷阱对GaAs mesfet I-V特性影响的建模
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499332
C. Fiegna, F. Filicori, G. Vannini, F. Venturi
{"title":"Modeling the effects of traps on the I-V characteristics of GaAs MESFETs","authors":"C. Fiegna, F. Filicori, G. Vannini, F. Venturi","doi":"10.1109/IEDM.1995.499332","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499332","url":null,"abstract":"This paper provides an investigation on the effects of deep level traps on the large-signal I-V characteristics of GaAs MESFETs by means of measurements and physics-based device simulations; results give clear indications that pulsed I-V measurements are sufficient in order to characterize large-signal AC device operation and provide a good physical basis for circuit-level large signal MESFET models.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A novel semimetallic quantum well FET 一种新型半金属量子阱场效应管
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499218
M. Yang, Fu-Cheng Wangt, C. Yang, B. R. Bennett, T. Q. Do
{"title":"A novel semimetallic quantum well FET","authors":"M. Yang, Fu-Cheng Wangt, C. Yang, B. R. Bennett, T. Q. Do","doi":"10.1109/IEDM.1995.499218","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499218","url":null,"abstract":"In this paper, we report unique three-terminal characteristics obtained from a semimetallic quantum well FET, which consists of two adjacent quantum wells, GaSb and InAs. As a result of their band alignment, both the two-dimensional (2D) electron gas and the 2D hole gas can coexist. With a standard FET structure, the 2D carrier concentration can be continuously tuned from >10/sup 12/ electrons/cm/sup 2/ to >10/sup 12/ holes/cm/sup 2/, when the gate voltage is varied from +8V to -8V. An efficient frequency-doubler utilizing this coupled dual-channel FET is demonstrated.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114556846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct tunneling N/sub 2/O gate oxynitrides for low-voltage operation of dual gate CMOSFETs 用于双栅cmosfet低压工作的直接隧道N/sub 2/O栅氮氧化物
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499350
T. Matsuoka, S. Kakimoto, T. Nakano, H. Kotaki, S. Hayashida, K. Sugimoto, K. Adachi, S. Morishita, K. Uda, Y. Sato, M. Yamanaka, T. Ogura, J. Takagi
{"title":"Direct tunneling N/sub 2/O gate oxynitrides for low-voltage operation of dual gate CMOSFETs","authors":"T. Matsuoka, S. Kakimoto, T. Nakano, H. Kotaki, S. Hayashida, K. Sugimoto, K. Adachi, S. Morishita, K. Uda, Y. Sato, M. Yamanaka, T. Ogura, J. Takagi","doi":"10.1109/IEDM.1995.499350","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499350","url":null,"abstract":"Dual gate CMOSFETs with high performance were successfully realized by using 2.8 nm N/sub 2/O-oxynitrides as gate dielectrics. Unlike other fabrication procedures, /sup 11/B/sup +/ ions instead of /sup 49/BF/sub 2//sup +/ were implanted into the gate electrodes of PMOSFETs. We demonstrated that boron diffusion through the 2.8 nm-oxynitrides is effectively blocked by the use of RTA. Substrate current due to hot-carrier effects was observed for NMOSFETs with T/sub ox/=2.8 nm and L=0.5 /spl mu/m even below 1 V. Gate-oxide leakage of surface-channel PMOSFETs is lower than that of NMOSFETs because of high barrier height for holes which significantly reduces hole direct tunneling compared with electron direct tunneling.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116304620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Thermal analysis of vertically integrated circuits 垂直集成电路的热分析
Proceedings of International Electron Devices Meeting Pub Date : 1995-12-10 DOI: 10.1109/IEDM.1995.499244
M. Kleiner, S. Kuhn, P. Ramm, W. Weber
{"title":"Thermal analysis of vertically integrated circuits","authors":"M. Kleiner, S. Kuhn, P. Ramm, W. Weber","doi":"10.1109/IEDM.1995.499244","DOIUrl":"https://doi.org/10.1109/IEDM.1995.499244","url":null,"abstract":"In this paper, a thermal analysis of Vertically Integrated Circuits (VIC) is presented for the first time. Based on a 1-D model, temperature differences in VICs of less than 10/spl deg/C are evaluated for most practical applications. Detailed 3-D investigations show that self-heating of MOSFETs in the upper chip-layers of a VIC is more pronounced than in bulk CMOS and that it strongly depends on the thickness of the silicon remaining in the chip-layer. In addition, thermal coupling between adjacent transistors is observed to be much more marked.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124705628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
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