CMOS process design for minimization of IC power consumption using TCAD

Abstract

CMOS low-voltage process design is presented as an example of industrial application of technology CAD. TCAD tools are used to evaluate G/sub P/, the gain in power efficiency (i.e. battery lifetime) which is achievable by reduction of supply voltage (V/sub dd/) with adaptation of threshold voltage (V/sub th/) and gate length scaling for constant performance. The trade-off between leakage and active power depending on the IC properties is studied. Maximum G/sub P/ found for a 16 bit microprocessor with 32 kB on chip SRAM is about 7 for V/sub th/ of /spl plusmn/0.3V and V/sub dd/ of 1.3V.