{"title":"利用TCAD设计CMOS工艺，使IC功耗最小化","authors":"A. von Schwerin, D. Schumann, J. Berthold","doi":"10.1109/IEDM.1995.499242","DOIUrl":null,"url":null,"abstract":"CMOS low-voltage process design is presented as an example of industrial application of technology CAD. TCAD tools are used to evaluate G/sub P/, the gain in power efficiency (i.e. battery lifetime) which is achievable by reduction of supply voltage (V/sub dd/) with adaptation of threshold voltage (V/sub th/) and gate length scaling for constant performance. The trade-off between leakage and active power depending on the IC properties is studied. Maximum G/sub P/ found for a 16 bit microprocessor with 32 kB on chip SRAM is about 7 for V/sub th/ of /spl plusmn/0.3V and V/sub dd/ of 1.3V.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CMOS process design for minimization of IC power consumption using TCAD\",\"authors\":\"A. von Schwerin, D. Schumann, J. Berthold\",\"doi\":\"10.1109/IEDM.1995.499242\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CMOS low-voltage process design is presented as an example of industrial application of technology CAD. TCAD tools are used to evaluate G/sub P/, the gain in power efficiency (i.e. battery lifetime) which is achievable by reduction of supply voltage (V/sub dd/) with adaptation of threshold voltage (V/sub th/) and gate length scaling for constant performance. The trade-off between leakage and active power depending on the IC properties is studied. Maximum G/sub P/ found for a 16 bit microprocessor with 32 kB on chip SRAM is about 7 for V/sub th/ of /spl plusmn/0.3V and V/sub dd/ of 1.3V.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.499242\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS process design for minimization of IC power consumption using TCAD
CMOS low-voltage process design is presented as an example of industrial application of technology CAD. TCAD tools are used to evaluate G/sub P/, the gain in power efficiency (i.e. battery lifetime) which is achievable by reduction of supply voltage (V/sub dd/) with adaptation of threshold voltage (V/sub th/) and gate length scaling for constant performance. The trade-off between leakage and active power depending on the IC properties is studied. Maximum G/sub P/ found for a 16 bit microprocessor with 32 kB on chip SRAM is about 7 for V/sub th/ of /spl plusmn/0.3V and V/sub dd/ of 1.3V.
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