Thermal analysis of vertically integrated circuits

Abstract

In this paper, a thermal analysis of Vertically Integrated Circuits (VIC) is presented for the first time. Based on a 1-D model, temperature differences in VICs of less than 10/spl deg/C are evaluated for most practical applications. Detailed 3-D investigations show that self-heating of MOSFETs in the upper chip-layers of a VIC is more pronounced than in bulk CMOS and that it strongly depends on the thickness of the silicon remaining in the chip-layer. In addition, thermal coupling between adjacent transistors is observed to be much more marked.