M. Ugajin, J. Kodate, Y. Kobayashi, S. Konaka, T. Sakai
{"title":"高f/sub T/和f/sub max/硅双极晶体管,采用超高性能超自对准工艺技术,用于低能耗和超高速LSI","authors":"M. Ugajin, J. Kodate, Y. Kobayashi, S. Konaka, T. Sakai","doi":"10.1109/IEDM.1995.499323","DOIUrl":null,"url":null,"abstract":"Very-high f/sub T/ (up to 50 GHz) and f/sub max/ (up to 70 GHz) silicon bipolar transistors have been developed using Ultra-high-performance Super Self-aligned process Technology (USST). This technology is characterized by drastically-scaled lateral dimensions and shallow, heavily-doped extrinsic base structures. USST greatly reduces base-collector junction capacitance and base resistance, and hence makes f/sub max/ about twice as large as SST1C technology without vertical scaling. The fabricated ECL circuits show a minimum gate delay of 16.5 ps at a switching current of I/sub CS/=1.0 mA/G.","PeriodicalId":137564,"journal":{"name":"Proceedings of International Electron Devices Meeting","volume":"55 25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's\",\"authors\":\"M. Ugajin, J. Kodate, Y. Kobayashi, S. Konaka, T. Sakai\",\"doi\":\"10.1109/IEDM.1995.499323\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Very-high f/sub T/ (up to 50 GHz) and f/sub max/ (up to 70 GHz) silicon bipolar transistors have been developed using Ultra-high-performance Super Self-aligned process Technology (USST). This technology is characterized by drastically-scaled lateral dimensions and shallow, heavily-doped extrinsic base structures. USST greatly reduces base-collector junction capacitance and base resistance, and hence makes f/sub max/ about twice as large as SST1C technology without vertical scaling. The fabricated ECL circuits show a minimum gate delay of 16.5 ps at a switching current of I/sub CS/=1.0 mA/G.\",\"PeriodicalId\":137564,\"journal\":{\"name\":\"Proceedings of International Electron Devices Meeting\",\"volume\":\"55 25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1995.499323\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1995.499323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's
Very-high f/sub T/ (up to 50 GHz) and f/sub max/ (up to 70 GHz) silicon bipolar transistors have been developed using Ultra-high-performance Super Self-aligned process Technology (USST). This technology is characterized by drastically-scaled lateral dimensions and shallow, heavily-doped extrinsic base structures. USST greatly reduces base-collector junction capacitance and base resistance, and hence makes f/sub max/ about twice as large as SST1C technology without vertical scaling. The fabricated ECL circuits show a minimum gate delay of 16.5 ps at a switching current of I/sub CS/=1.0 mA/G.