2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献_第7页

Alternative dicing die attach film method for high volume small dice application 可选择的切片模具贴膜方法，适用于大批量小切片应用

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746668

Kf Lim

引用次数: 0

High temperature storage performance for Au Sn diffusion soldering on Cu leadframe substrate 铜引线框架基板上Au - Sn扩散焊的高温储存性能

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746718

Z. Abdullah, Mohamed Abdul Rahman

引用次数: 0

Frequency and time domain characterization of substrate coupling effects in 3D integration stack 三维积分叠加中衬底耦合效应的频域和时域表征

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746730

E. Eid, T. Lacrevaz, C. Bermond, S. Capraro, J. Roullard, B. Fléchet, L. Cadix, A. Farcy, P. Ancey, F. Calmon, O. Valorge, P. Leduc

引用次数: 2

FMEA/PFMEA : What they never teach you in formal school FMEA/PFMEA:正规学校从来没有教你的东西

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746755

S. Shridhar

{"title":"FMEA/PFMEA : What they never teach you in formal school","authors":"S. Shridhar","doi":"10.1109/IEMT.2010.5746755","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746755","url":null,"abstract":"FMEA or Failure Mode Effects Analysis is an analytical procedure to identify and minimize risk factors in product and process designs. Whilst the FMEA methodology has been in use since the 1940's, the effectiveness of the procedure became really widespread after its adoption by the automotive industry in the late 1970's. The FMEA procedure is a preventative tool and hence must be performed prior to finalization of the design of the product and the manufacturing or service processes. Quality Assurance Standards such as ISO 9001 and TS 16949 emphasize the need for minimizing and /or eliminating risks in the design of products and processes, which has led to many organisations adopting the FMEA methodology as part of their D & D processes. This widespread use is encouraging, but equally important is the correct use of the procedure as otherwise the resultant documentation will not provide the required focus in the detection of risks. The use of robustness tools such as the Boundary diagram, Parameter diagram and the Interface matrix is essential in order to bring in the required discipline in the detection of risk factors. Experience shows that engineers often focus only on those aspects that they control directly and miss the causal factors, particularly the interfaces in the system, misuse of the product by the customer - either intentional or unintentional, and natural degradation, all of which cause the risks. In this article, the author explains how the robustness tools can be usefully applied in both the design and manufacturing design of products such as semiconductor packaging.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130720573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The development of new SMT printing techniques for mixed technology (heterogeneous) assembly 为混合技术(异质)组装开发新的SMT印刷技术

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746678

M. Whitmore, C. Ashmore

引用次数: 6

A consideration on the Electrical Overstress(EOS) failure mechanism in the interconnection system of liquid crystal display(LCD) panel 液晶显示器(LCD)面板互连系统中电气超应力(EOS)失效机制的思考

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746676

Jae-Hyung Kim, Dong-Nam Kim, Hoon Jang, Young-Chul Jo, Nam-Yong Kim, Seung-Geun Kang, Byung-Ju Lee, Dal-Soo Kim

引用次数: 1

Miniaturization innovation evolution of electronics packaging - What's coming next …? 电子封装的小型化创新演变——接下来会发生什么?

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746749

A. Wagiman

引用次数: 1

3D Packaging Technology: Enabling the next wave of applications 3D封装技术:开启下一波应用浪潮

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746735

M. A. Bolanos

{"title":"3D Packaging Technology: Enabling the next wave of applications","authors":"M. A. Bolanos","doi":"10.1109/IEMT.2010.5746735","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746735","url":null,"abstract":"This paper describes 3D Packaging Technology trend and highlights its contribution to the development of the next wave of electronic products. The paper's introduction discusses general Packaging Technology trends in the semiconductor industry and the major Packaging Functionality changes that have been experienced during the last few decades. It also covers some of the future functions that will be performed by packaging technology such as system in packages to enable autonomous smart electronics, with heterogeneous technology such as signal processing, sensors, power management, energy harvesting modules and nano storage devices. It describes the evolution of 3D packaging technology in three different waves or phases. It also presents some of the Megatrends enabled by 3D Packaging, Miniaturization and Integration, as well as the main challenges the industry is experiencing with the development and implementation in volume production of the third wave, Through Silicon Vias (TSV). The final section of this paper discusses TSV drivers and benefits, the expected Value Added coming from TSV vs. Required Cost to Develop and Implement, and whether TSV is going to be used in mostly “Niche High Value Added” applications or adopted as a Mainstream solution for many applications.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131179014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Filler size influence on moldabilty of high density QFN package 填料尺寸对高密度QFN封装成型性能的影响

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746696

C. Yi, K. Ong, Q. Pin, Lee Swee Kah

引用次数: 1

Resolving thermal resistance problem of Analog device in conjunction with the ONxx Shrink Die Technology 结合ONxx缩模技术解决模拟器件的热阻问题

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746704

Y. G. Yabut, A. Reyes

引用次数: 0