2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献

{"title":"Electroless over pad metallization for high temperature interconnections","authors":"S. Qu, K. Pham, L. Nguyen, A. Prabhu, A. Poddar, S. Athavale, A. Xu, Y. C. How, C. Lee, K. C. Ooi","doi":"10.1109/IEMT.2010.5746709","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746709","url":null,"abstract":"Electrolessly plated over pad metallization (OPM) was evaluated for high temperature gold wire bonding applications. Bonding strength, measured by wire bond bump shear test, of 4N gold wire on electroless OPMs, such as electroless nickel/immersion gold (ENIG), electroless nickel/electroless palladium (ENEP), and electroless nickel/electroless palladium/immersion gold (ENEPIG), was carefully evaluated before and after wire bond was subjected to various environmental stresses. Failure modes, besides bonding strength, were particularly examined for overall bonding quality assessment and OPM screening. Authors' intensive work found that ENEPIG OPM had the highest bonding strength and consistent failure mode over the other two OPM options: ENIG and ENEP. Even after 3000 hours of 175 °C high temperature storage life test, there is no sign of bonding strength degradation.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122861766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Measurement of thermal resistance of TIMs, heat sinks and interfaces in thermal management systems for IC packages","authors":"S. Somasundaram, A. Tay","doi":"10.1109/IEMT.2010.5746715","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746715","url":null,"abstract":"With the trend towards ever-powerful chips and evermore-intense heat fluxes, the thermal resistance of interfaces is becoming an important consideration. Thermal interface materials (TIMs) are playing a critical role in the thermal management of advanced chip packages. While the thermal conductivity of TIMs may be relatively easily measured in the laboratory, it is often not easy to establish the value of the thermal resistance of the assembled TIM in an actual package. This is because the thermal resistance of the TIM in an actual package depends on several parameters including bond line thickness, presence of voids, uniformity of bond line and quality of adhesion between TIM and contact surfaces. Hence, it is imperative to establish an easy-to-use and accurate method for evaluating the thermal resistance of TIMs, heat sinks and interfaces in thermal management systems for IC packages. This paper describes the use of a thermal transient method for the characterization of the TIMs of two different functional chip packages, which incorporate integrated heat spreaders. The overall junction to ambient thermal resistance of the packages was also determined. Three different tests were conducted on each package - natural convection test, natural convection with a passive heat sink and forced convection with an active heat sink. In the tests, a step change in heat input to the chip was applied and the resulting thermal transient response of the package was measured every microsecond until equilibrium was reached. The thermal transient profile was then analysed to obtain the structured functions, thermal resistance of the TIM and the junction-to-ambient thermal resistance. The paper also describes the thermal resistance, and hence heat transfer coefficients of surfaces, which are cooled by spray cooling. It is concluded that a quick transient testing after the completion of packaging can serve as a reliability tool to ensure if all the parts of a package are assembled properly and will also provide values of parameters such as thermal resistance of TIMs and junction-ambient thermal resistance.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116952387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved corner rounding method for trenched MOSFET","authors":"N. H. Seng","doi":"10.1109/IEMT.2010.5746769","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746769","url":null,"abstract":"This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance. However, the direct implementation of the SACOX on the deep trenched MOSFET having less than 0.5 um trench width is insufficient to eliminate the oxide thinning at the concave corners. The experimental results including the scanning electron microscopy (SEM) images are presented to illustrate how the sharp corners vanish. The concave corners are encompassed by a smooth layer of silicon dioxide served as a gate oxide for vertical trenched MOSFET. Electrical measurement shows that the breakdown voltage was improved by eliminating the gate oxide weak spots","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116983913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation- measurement correlation study of single ended interfaces by using Signal Integrity and Power Integrity co-simulation","authors":"L. Chuan, Wong Tai Loong","doi":"10.1109/IEMT.2010.5746695","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746695","url":null,"abstract":"Signal Integrity (SI) and Power Integrity (PI) issues are the major concern for high speed design in Electronics Industries these days. Currently, SI and PI analysis is done mostly independently and even though some indirect considerations of each other might be taken during analysis, these SI and PI behaviors doesn't always sum up linearly. This results in very pessimistic designs which does not longer applicable in today's challenging and cost efficient world. Therefore it is crucial to do SI and PI co-simulation in order to achieve lower voltage, higher current and yet cheaper design. In this paper, SI-PI co-simulation has been performed on General Purpose Input Output (GPIO) of interfaces of Intel's latest flip chip chipset. This project's scope also includes lab activities to correlate and validate our simulations results. The most important of all, the findings and lessons learned from this project will also be shared. This information contains valuable and essential data that can be proliferated into future designs to make more robust, competitive and cost effective product.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124588694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tombstone reduction by reflow profile optimization, SMT stencil design and pad design","authors":"H. Ming, Tan Kong Ming, L. Khor","doi":"10.1109/IEMT.2010.5746716","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746716","url":null,"abstract":"With the technology advancing, most products are getting more personalize with various variety. Hand held products that are larger than palm size has no longer favor one's interest; the miniature product is the future, its means smaller, lighter and portable. Miniaturization product can be succeeded by reducing package size and the integration of ultra-small component (0402, 0201, 01005). SIP-MCM (system in package-multichip module) is one of the technologies that involve; this package is built with the combination of multiple dies and miniature passive components in SMT processes. In SMT process, small chip components prone to have tombstone defect","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116160086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leaded module - steering the next industry trend for best in class thermal performance and ease of use","authors":"Woo Kuan Yee, L. Meng, Eugene Lee","doi":"10.1109/IEMT.2010.5746738","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746738","url":null,"abstract":"Leveraging semiconductor industry trend today, there is a massive growing demand for module package at end customers' application. This is essentially due to benefits from system in package as a complete solution for ease of use, miniaturization, enhanced thermal, EMI shielding and low cost IC packaging.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123935730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of wafer sawing capability on 2 mil saw street 4 mil thickness with TiNiAg back metal","authors":"Siew Han Looe, Sw Wang","doi":"10.1109/IEMT.2010.5746664","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746664","url":null,"abstract":"For existing industrial trend, increasing the Potential Die per Wafer (PDPW) through saw street reduction has become the common practice for wafer manufacturing cost reduction, which meant that sawing on wafer with saw street as narrow as 2 mil has become an important wafer sawing process in the market. The sawing process is becoming more complex with the requirement of multi layer wafer back metallization, such as TiNiAg. This paper reports the successful of development of wafer sawing capability on 2 mil saw street 4 mil thickness with TiNiAg Back Metal. The success of this sawing capability has created the opportunity not only for wafer cost reduction, but also provides a solid base and reference for the development of more challenging sawing process in future. This paper describes the development of the sawing capability.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126966934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer sort yield improvement by localizing and applying optical proximity correction on a metal bridging issue","authors":"Russell M. Dumlao, Karsten P. Ulland, M. Marcos, D. Beasterfield","doi":"10.1109/IEMT.2010.5746702","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746702","url":null,"abstract":"This paper presents a wafer sort yield improvement on a device through changes in the optical proximity correction (OPC) algorithm. Failure analysis of the device showed metal bridging in a specific metal feature which caused gross functional failures in scan tests. Localizing the metal bridging was done by liquid crystal thermal analysis (LCTA) and device layout comparison. Sub-minimum spaces between metal lines were discovered in this metal layer that was created by an interaction between the existing OPC algorithm and a specific feature of two adjacent traces. Simple Boolean algorithms are added to the existing algorithm to correct the metal bridging to remove this final spacing issue and any others like it. This study reports a wafer sort yield improvement of 30% due to the OPC fix.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127047075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Current technology barriers and future direction for packaging","authors":"Y. Tsukada","doi":"10.1109/IEMT.2010.5746763","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746763","url":null,"abstract":"Two decades have passed since the introduction of packaging technology with underfill reinforced flip chip bonding and organic chip carrier. The high performance and low cost packaging technology has been facing serious barriers for moving to the next generation. What should be the ranges of joint and wiring ground rules to shoot for the next step? What are the issues for moving to the step and does any solution exists for each issues? How to resolve the barrier for the cost? What is the area to contribute to the environmental issues after Pb free solder? Current status of such questions and direction for the future will be discussed.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extending the technology envelope of equipment fungibility with single minute exchange die (SMED) novel solution","authors":"Octovia Peter","doi":"10.1109/IEMT.2010.5746771","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746771","url":null,"abstract":"Semiconductor manufacturing is trending to become more competitive and fast-paced in achieving efficient productivity. While striving to meet the goal of minimizing complexity and cost reduction, the challenges for equipment end user are maximizing its functionality and flexibility. With higher product volumes and increasing number of products requiring unique equipment configurations, it is sound to explore the opportunity on enhancing the features of the equipment to be fungible upon capacity requirement changes, and enable a reduction in dedicated buffer capacity. This paper describes how SMED approach is implemented into the rapid changeover process of an equipment in which the fungibility constraint of equipment features were identified and analyzed. The techniques of SMED approach has not only benefit in equipment flexibility but also the process improvement.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125935781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}