当前包装的技术壁垒与未来发展方向

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI:10.1109/IEMT.2010.5746763

Y. Tsukada

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引用次数: 0

摘要

自采用下填充增强倒装芯片键合和有机芯片载体的封装技术以来，已经过去了二十年。高性能、低成本的封装技术一直面临着向下一代发展的严重障碍。下一步拍摄的接头和布线的基本规则应该是什么?进入该步骤的问题是什么?每个问题是否存在任何解决方案?如何解决成本障碍?在无铅焊料之后，对环境问题有何贡献?讨论这些问题的现状和未来的发展方向。

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Current technology barriers and future direction for packaging

Two decades have passed since the introduction of packaging technology with underfill reinforced flip chip bonding and organic chip carrier. The high performance and low cost packaging technology has been facing serious barriers for moving to the next generation. What should be the ranges of joint and wiring ground rules to shoot for the next step? What are the issues for moving to the step and does any solution exists for each issues? How to resolve the barrier for the cost? What is the area to contribute to the environmental issues after Pb free solder? Current status of such questions and direction for the future will be discussed.

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2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)

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