2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献

{"title":"Chipping free process for combination of narrow saw street (60um) and thick wafer (600um) sawing process","authors":"Mohd Amri, David Liew, F. Harun","doi":"10.1109/IEMT.2010.5746667","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746667","url":null,"abstract":"Chipping free is a dream for wafer sawing process. With current high complexity of wafer technology plus the drive for cost reduction by narrowing the saw street width, it is a challenge which requires huge effort for wafer sawing process to achieve chipping free process. Higher density of metallization causing higher blade loading during mechanical sawing. This leads to chipping penetrating under the guard ring and damaging the active area. This paper will share all the activities towards chipping free process on a device involving optimization through mechanical sawing, infra red camera and laser grooving process. Blade selection involving various diamond grit size, different concentration, slit design and low k types only able to minimize the occurrence but not totally eliminate it. Finally by performing laser grooving, significant results were achieved with zero chipping occurrences. In addition, suitable laser frequency selection is also important to ensure the best performance. In this case higher frequency laser grooving in combination with mechanical sawing process found to be able to meet the requirement.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127197084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wire sweep characterization of multi-tier copper wire bonding on thermally-enhanced plastic ball grid array packages","authors":"S. Teh, By Low, C. Foong, CT Siong","doi":"10.1109/IEMT.2010.5746745","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746745","url":null,"abstract":"Copper (Cu) wire bonding is the most viable alternative interconnection technology to gold (Au) wire bonding when cost is considered. Recent developments in bonding technology and capability has resulted in copper wire bonding being targeted at high pin count and high performance applications such as ball grid array packages. Wire sweep performance is extremely important in high I/O products as slight increase in wire sweep may result in wire shorting and eventually losing the functionality of the devices. The gap is especially apparent in multi-tier high pin count ultra fine pitch (40µm) copper wire bonding packages. In this study, wire sweep characterization was performed using two types of 4N 18µm copper wires from two different suppliers. Existing 18µm Au wire from production was used as control. The test vehicle used in this study was a high pin count thermally enhanced plastic ball grid array (TEPBGA) 31mm×31mm package with 689 ball counts. The wire sweep performance of the different Cu wire types at various wire locations using the current production molding compound were also investigated. Wire sweep results showed that Cu wire type A had significant lower wire sweep (approximately 0.5%) compared to current Au wire. However, Cu wire type B showed comparable wire sweep performance as current production Au wire. In summary, wire sweeping resistance of copper wires are strongly dependent on the fabrication processes and heat treatments of the respective wire suppliers. Moreover, it was found that wire sweep percentage was very much influenced by wire locations during transfer molding process.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Heterogeneous integration - A key enabling technology","authors":"R. Aschenbrenner","doi":"10.1109/IEMT.2010.5746757","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746757","url":null,"abstract":"Advanced silicon technologies offer the possibility of integrating hundreds of millions of transistors in a single electronic component such as a microprocessor. Experts predict that the increase of components per chip will follow the well known “Moore's law” in the next decade, too. “Microelectronics” will become “Nanoelectronics”. This trend can be characterized by “More Moore”. If electronic signal and data processing systems are focussed, nanoelectronic components will be very cost efficient due to larger wafer sizes and a high degree of miniaturization (System-on-Chip). But future multifunctional systems require not only more signal and data processing power but also require interfaces to the human sensory organs and altogether functions for an interaction with the environment. Besides these, antennas, components for optical signals and data transmission as well as functions for energy conversion and storage are also needed.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125065373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A study of deep body implant into the base of Vertical NPN bipolar transistors","authors":"Changgui Tan, C. Siong, H. M. Reza, Hwang Chee Siang","doi":"10.1109/IEMT.2010.5746737","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746737","url":null,"abstract":"In this paper, we demonstrate the sensitivity of base resistance by different tilt angle of deep body implant into the base of Vertical NPN bipolar transistors. The base resistance in the vertical NPN bipolar transistors shows a strong dependency on the tilt angle of the boron implant from the deep body. We are able to improve the Early voltage (VEA) without degrading the current gain and breakdown voltage of collector and base on an optimal tilt angle of 0 degree.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"2 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123711738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Built In Self Test (BIST) Survey - an industry snapshot of HVM component BIST usage at board and system test","authors":"Z. Conroy, H. Li, J. Balangue","doi":"10.1109/IEMT.2010.5746723","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746723","url":null,"abstract":"With board and component technology and integration rapidly increasing and becoming more complex, the testing of boards standalone and in a system is becoming more difficult, time consuming and costly. This paper addresses integrated circuit (IC) Built In Self Test (BIST) usage at the board and system test levels to provide increased test coverage, reduced test time and cost. This paper presents the results of an IC BIST usage survey developed by the International Electronics Manufacturing Initiative (iNEMI). The survey was intended to gauge the current adoption rate of IC BIST for board and system test, identify any impediments to widespread use, and select areas for future research.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An analysis on oxidation, contamination, adhesion, mechanical stress and electro- etching effect toward DIP package delamination","authors":"W. Teng, Heng Chai Wei","doi":"10.1109/IEMT.2010.5746700","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746700","url":null,"abstract":"Package delamination forms a separation layer in between mold compound to chip, die paddle and leads, which subsequent affects ground bond quality and degrades package electrical performance. This paper focuses on the interaction relationship of each assembly process towards lead delamination in Dual in Line (DIP) package. No ground bond delamination is allowable to ensure the package robustness. An experiment was conducted to characterize and understand the effect of assembly-induced lead delamination. The identified critical processes include the staging time control from die placement to curing after die bond, contamination of volatile outgassing from epoxy A in poor air oven circulation during epoxy curing, thermal oxidation, mold compound wettability on leadframe during molding, electro-etching effect from deflashing as well as mechanical force from singulation were investigated. Electrolytic deflashing has identified as the primary root cuase of lead delamination due to electro etching effecct. Secondary factor to further increase the lead delamination is poor mold compound to leadframe adhesion due to imbalance mold flow, mechanical force from singulation and severe copper oxidation. Improved mold tooling concept will be beneficial to further minimize the imbalance mold flow between the top mold and bottom mold. Chemical dipping without electric current is recommended as promising lead delamination results and is reflected in C-SAM (Scanning Acoustic Miscoscope).","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126667190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and modelling of a 40W microwave switch in QFN 2×2 package","authors":"Chin-leong Lim","doi":"10.1109/IEMT.2010.5746705","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746705","url":null,"abstract":"A 40W PIN diode switch in QFN2×2 package have been characterized and modelled. The design fulfilled the requirements for a medium-power microwave switch in a small, inexpensive plastic package. The thermal performance is comparable to that of more expensive ceramic devices.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128127457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approaches and developments in MEMS power harvesting generators","authors":"M. D. Shaker, H. Salleh","doi":"10.1109/IEMT.2010.5746698","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746698","url":null,"abstract":"This paper presents designs and optimizations for two types of micro electromechanical generators system, first one is the narrow band generators which have a particular resonant frequency the second one is wide band generators (tunable generators) where the resonant frequency can be controlled by adjusting the cantilever length, changing the distance between magnets, and etc. The work and developments done by researchers are presented and for comparison, their results are listed below: The Laser-micro generator was fabricated with a total volume of 1cm3, output power of ∼830µW, frequencies (60 – 110) Hz. The output power of the (body-worn) generator was 2–25 µW, volume of 0.25 cm3. The vibration-powered generator for intelligent sensor systems has an overall volume of 0.84 cm3 with an average power of 157 µW when tested on a car engine. One type of Paddle generator produced an output power of 2 mW at a frequency of 9.81 kHz. In the frequency sweeper generator, the device generates 0.4 µW with frequency range of 4.2–5 kHz. For Tunable energy harvesting piezoelectric cantilever generator, a natural frequency was successfully tuned over a frequency range of 22–32 Hz to produce power output of 240–280 µW. The resonant frequency of the vibration-based electromagnetic micro-generator was tuned from 67.6 to 98 Hz to produce a power of 61.6–156.6 µW. The tuning of the wide band generators seemed to be effective.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114527575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigations of the effects of blade type, dicing tape, blade preparation and process parameters on 55nm node low-k wafer","authors":"K. Shi, K. Yow, Rachel Khoo","doi":"10.1109/IEMT.2010.5746663","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746663","url":null,"abstract":"This paper presents an investigation of the effects of blade type, dicing tape, blade preparation and the key process parameters optimization on improving topside ILD peeling (thicker scribe structures) and chipping for 55nm low-k wafer. An appropriate dicing blade selection, blade preparation / conditioning methodology and dicing tape selection plays an important role in developing a robust saw process. As such, experimental studies were conducted under varying Z1 spindle rotation, Z1 cut depth into Si as well as the blade type property variation as the input factors, in order to improve the ILD peeling and die chipping. The settings of machining parameters and blade types were determined by using the design of experiment (DOE) techniques and the critical process parameters and materials were analyzed statistically by using the analysis of variance (ANOVA). Dicing tape property variations (PO-base or PVC-base) as well as the blade preparation methodology posed some influences on the overall dicing quality, such as die backside chipping, die removal performance, ILD peeling and die topside chipping. SEM imaging and optical visual inspection were conducted to validate the impacts of the ILD peeling / chipping on post-processed low-k wafers. A thorough quantification and categorization of ILD peeling and chipping on heavy metallization at the saw scribe structures were described. As part of the recommendation for future works, a different approach in dicing technology, namely laser grooving was proposed to eliminate ILD peeling and chipping. In conclusion, the optimized dicing recipe for 55nm node low-k wafer suggested by the DOE model are: (1) a thinner PO-base dicing tape, (2) a dicing blade with higher diamond concentration and finer grit size, (3) blade preparation / conditioning done with SiC board and (4) processing at lower spindle rotation and deeper cut depth are much preferred. The overall dicing responses and cutting quality has improved and is better compared to current production recipe.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126112162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges in copper 2nd bond quality on nickel palladium leadframe","authors":"Tan Kian Heong, F. Harun","doi":"10.1109/IEMT.2010.5746750","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746750","url":null,"abstract":"Nickel-palladium (NiPd) based lead finishes has been one of the options for lead-free electronics. Currently there are different types of NiPd finish in the industry like NiPdAuAg, NiPdAu and rough NiPdAuAg. These preplated lead frame finishes while eliminate the need for plating after assembly/encapsulation, it also has a few challenges especially on the 2nd bond wire bond quality. This is especially obvious when Cu wire bond was introduced. This paper will provide some insight, compare the 2nd bond performance when using Cu wire on both Ag plated frame and NiPd frame. It was observed that stitch pull strength for Cu wire bonding on rough uppf lead frame generally lower than the Ag plated Cu lead frame and percentage of Cu remain after stitch pull for rought µppf lead frame is lesser than the Ag plated lead frame. The different results possible due to different lead frame plating materials, plating thickness and hardness.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127169207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}