2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献_第9页

Packaging trends in mobile electronics - Towards wafer level packaging 移动电子的封装趋势-迈向晶圆级封装

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746764

X. Baraton

引用次数: 0

Small signal electrical testing in package engineering 封装工程中的小信号电气测试

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746762

C. S. Liu

引用次数: 1

Cu wire bonding on Cu-Ni-Pd bond pad and leads: From development to robust production Cu- ni - pd键合垫和引线上的铜线键合:从开发到稳健生产

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746742

Hanafi Said

引用次数: 0

RF shields that can be integrated with IC test handlers 可与IC测试处理器集成的射频屏蔽

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746724

Chin-leong Lim

引用次数: 0

Automotive electronics - Packaging as enabler technology 汽车电子。封装技术

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746761

Andreas Knoblauch

引用次数: 0

Color detection for vision machine defect inspection on electronic devices 电子设备视觉机缺陷检测中的色彩检测

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746681

P. Abrial, Y.L. de Meneses, Peeyush Bhatia

引用次数: 2

Innovation and collaboration - Keeping up with market demands and transitions 创新与协作——紧跟市场需求和转型

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746760

K. Hyland

引用次数: 0

2nd level reliability drop test robustness for Wafer Level Packages 晶圆级封装的二级可靠性跌落测试稳健性

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746686

Q. Pin, H. Ludwig, Y. W. Wei

{"title":"2nd level reliability drop test robustness for Wafer Level Packages","authors":"Q. Pin, H. Ludwig, Y. W. Wei","doi":"10.1109/IEMT.2010.5746686","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746686","url":null,"abstract":"2nd level reliability performance during drop impact is critical for Wafer Level Packages (WLP). Accompanying the popularization of portable and mobile phone products, high reliability under board level drop test is a great concern to semiconductor manufacturers. A 0.4mm pitch Cu under bump metallization (UBM) type has been developed for mobile computing application. In this paper presents the impact on solder joint reliability with various approaches to achieve higher Drop Test (DT) robustness. Polymer Core solder ball, solder ball Sn1.2AgCu (additive Ni + α), polymer flux with SAC107 solder ball, solder ball Sn1.2Ag0.5Cu (doped), copper core solder ball, and additional 6µm passivation layer (polyimide) have been investigated. The test vehicles were 49 pins and 0.4mm ball pitch with Cu UBM. Ball shear test was carried out to measure the solder joint performance after reflow process and units were performed cross sectioned for IMC formation analysis. Board level drop test was performed as per JESD22-B111 test method. The drop test results showed polymer core solder ball gives the best performance which is more than 1000 drops, followed by Sn1.2Ag0.5Cu (doped) solder ball, polymer flux, additional 6um polyimide, Sn1.2AgCu (additive Ni + α) solder ball & copper core solder ball. It indicated the stress relaxation within IMC & strength improvement to achieve higher drop test performance for polymer core solder ball during drop test. On the other hand, copper core solder ball has the worst drop performance (66 drops) as it has rigid material (Cu) inside the ball and less solder amount that can absorb the drop impact and stress.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128819975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Thermal simulation study of die attach delamination effect on TQFP package thermal resistance 模具附着层脱层对TQFP封装热阻影响的热模拟研究

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746669

L. Meng, Eugene Lee, Mak Chee Hoe

{"title":"Thermal simulation study of die attach delamination effect on TQFP package thermal resistance","authors":"L. Meng, Eugene Lee, Mak Chee Hoe","doi":"10.1109/IEMT.2010.5746669","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746669","url":null,"abstract":"Delamination in semiconductor plastic packages often happens in many interfaces within the package itself, which is mainly caused by coefficient of thermal expansion (C.T.E) mismatch between the interfaces of two materials within the package. Die attach delamination is the separation between the silicon die and die attach pad on leadframe. Die attach delamination will reduce the total area of silicon die attached to pad and it is known to have increase the thermal resistance of the package. This could lead to early thermal shutdown of a device which uses exposed pad to dissipate heat. This paper is to investigate the die attach coverage effect on the package thermal resistance. A thermal modeling was done on various % of epoxy coverage to evaluate package thermal resistance. TQFP 100L with and without exposed pad are used for this model. Results show that die contact area to the pad will significantly affect the package thermal performance, especially at high power application. Package with exposed pad design will have higher increase of θja than non exposed pad in the event of die attach delamination.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125623471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Integrated nCTF pad design on PCB for BGA solder joint reliability enhancement PCB上集成nCTF焊盘设计，提高BGA焊点可靠性

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746685

Fook Loon Wooi, Ooi Ing Chuan

{"title":"Integrated nCTF pad design on PCB for BGA solder joint reliability enhancement","authors":"Fook Loon Wooi, Ooi Ing Chuan","doi":"10.1109/IEMT.2010.5746685","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746685","url":null,"abstract":"In PCBA manufacturing industry, corner adhesive was commonly used on BGA(Ball Grid Arrays) to resolve the solder joint crack induced by mechanical stress either during shock and vibration reliability test or during board manufacturing processes(ICT test fixture, router, handling and etc) especially for mobile motherboard. However, this solution imposed high manufacturing cost which required additional glue processes with more process control, additional equipment setup for adhesive dispenser and curing oven as well as additional material cost for the adhesive. Besides that, the BGA with corner adhesive is difficult to be reworked especially for high-temperature curing adhesive. A new approach in PCB design for BGA called integrated nCTF(non critical to function) or dummy pad has been developed to replace the costly corner adhesive to address the problem of solder joint crack induced at post board level shock and vibration reliability test as well as time-0 solder joint crack induced by mechanical stress during board manufacturing. This paper will review the land pattern of the integrated nCTF pad design, stencil opening design, evaluation plan and the results of CTF(critical to function) solder joint crack percentage comparison between integrated nCTF pad and individual nCTF pad as well as to show the bulky solder joint formed on the integrated nCTF pads.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124026477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1