2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献

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Impact of molding parameters on PBGA warpage characteristic 成型参数对PBGA翘曲特性的影响
L. W. Keat, Quah Chin Aik, L. C. Kan, Leehu Loon
{"title":"Impact of molding parameters on PBGA warpage characteristic","authors":"L. W. Keat, Quah Chin Aik, L. C. Kan, Leehu Loon","doi":"10.1109/IEMT.2010.5746693","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746693","url":null,"abstract":"PBGA (Plastic Ball Grid Array) has been around for years as the leading packaging technology for I/O controller. Occasionally PBGA package exhibits surface mount issues, typically the solder bridging, at very low defect per million. A series of investigation was carried out to address the key design modulators. This paper discussed the findings of how molding temperature could modulate the dynamic warpage characteristic of a PBGA package. Apart from design factors, the molding temperature plays significant role in reducing warpage at reflow temperature.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123878307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A reliable low cost assembly technology for 0201 compatible QFN, X3 Thin QFN 一种可靠的低成本组装技术,适用于0201兼容QFN, X3 Thin QFN
W. Law, Nicole Yong, Sh Liew, Daniel Phuah, K. Chung, Pn Ng
{"title":"A reliable low cost assembly technology for 0201 compatible QFN, X3 Thin QFN","authors":"W. Law, Nicole Yong, Sh Liew, Daniel Phuah, K. Chung, Pn Ng","doi":"10.1109/IEMT.2010.5746672","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746672","url":null,"abstract":"Electronics devices nowadays, especially the portable consumer devices like notebooks, GPS, multimedia players, digital cameras, camcorders, cellular phone handsets and accessories, are increasingly driving product demand and technological developments. Each succeeding product generation is expected to be smaller and lighter in weight, driving the needs of miniaturization technologies.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The importance of reliability in electronics 可靠性在电子产品中的重要性
J. Fjelstad
{"title":"The importance of reliability in electronics","authors":"J. Fjelstad","doi":"10.1109/IEMT.2010.5746759","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746759","url":null,"abstract":"The electronics industry has prided itself on the reliability of its products over the years and steady improvements have been made over the years. However, in recent times, there has been a slow but noticeable retreat from the long established trend. Unfortunately, such subtle changes in terms of lesser reliability will have far reaching effects on the global electronics industry and the environment. This presentation will examine the some of the history of reliability of electronics and speak to some of the technologies that have advanced the cause over the years. It will also explore how economics have influenced attitudes as to the importance of reliability and how well intended environmental legislation may be having some unintended consequences that are lessening reliability. The presentation will conclude with some thoughts on the current trends and their potential impact and how the electronics industry might renew its thinking relative to the importance of the reliability of its products.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123250716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Past, present and future of electronic packaging 电子封装的过去、现在和未来
J. Fjelstad
{"title":"Past, present and future of electronic packaging","authors":"J. Fjelstad","doi":"10.1109/IEMT.2010.5746773","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746773","url":null,"abstract":"As the first interconnection element after the semiconductor chip itself, IC packaging technologies are the primary gate keepers of electronic system performance. There are a myriad of different types of packages available, each normally targeted for a specific range of semiconductor devices. With so many options, understanding the basics of IC packaging - how they are constructed, what drives cost and what limits performance - is critical to the successful product design. Some of the most common IC packages, from chip scale to BGA packages as well as some of the many 3D stacked and folded structures, will be reviewed and discussed. The instructor will also review wafer level packaging. Finally, a look at the future of IC packaging will be provided to stimulate thought on how to actively engage and direct the future of IC packaging in mindful ways.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121047231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Environmental friendly package development by using copper wirebonding 利用铜线键合技术开发环保型封装
C. Gan, T. Toong, CP Lim, Cy Ng
{"title":"Environmental friendly package development by using copper wirebonding","authors":"C. Gan, T. Toong, CP Lim, Cy Ng","doi":"10.1109/IEMT.2010.5746747","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746747","url":null,"abstract":"This paper focuses on the 1.0 mil Cu wire development and its reliability performance mainly at component level of a BGA wire bond package which consists of 2 metal layer organic substrate more than 500 pin counts. This paper covers package reliability tests such as THB (Temperature and Humidity Biased test), unbiased HAST, TCB (temperature cycling B), high temperature storage tests on BGA laminate with 1.0 mil 4N bare Cu wire. Selection of best package BOM was based on component reliability test and also assembly process data collected during the evaluation. Therefore selection of BOM is not solely based on reliability performance but also its process feasibility and manufacturability. Comprehensive experimental analysis has been carried out to determine the bill of materials for the most robust Cu wire bonding process and reliability performance. Failure analysis on the unbiased HAST failure unit was carried out to understand the failure mechanism and benchmark to the industrial finding. Final reliability validation based on the selected BOM and process condition was conducted and results have been covered in this paper. In addition, comprehensive ongoing reliability monitoring program and yield monitoring have been established to ensure flawless production implementation and package reliability of Altera's Cu wirebond BGA laminate package.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114672183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Flip chip technology 倒装芯片技术
Y. Tsukada
{"title":"Flip chip technology","authors":"Y. Tsukada","doi":"10.1109/IEMT.2010.5746775","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746775","url":null,"abstract":"2. Elements of design and manufacturing Chip and carrier bumping Joint and substrate Underfill and cooling 3. Packaging configuration BGA and SiP (MCM) Wafer Level package Known Good Die 4. Reliability and life Stress test and life estimation Typical failure mode Failures factorial analysis 5. Current issues for density increase Thermal stress Joint fatigue life Joint electro-migration 6. Requirement for new materials and future direction 2D packaging joint and substrate 3D chip stack packaging Optical/Electrical packaging 7. Japanese packaging technology trend (Special Topics) SiP, WLP, PoP, Embedded component Product miniaturization.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126594032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Study on IMC morphology and impact to solder joint performance for different halogen free (HF) flux in semiconductor application 半导体应用中不同无卤助焊剂对IMC形貌及焊点性能影响的研究
Ooi Wan Koon, M. Razai, Chan Boon Pin, N. Mohd Sharif
{"title":"Study on IMC morphology and impact to solder joint performance for different halogen free (HF) flux in semiconductor application","authors":"Ooi Wan Koon, M. Razai, Chan Boon Pin, N. Mohd Sharif","doi":"10.1109/IEMT.2010.5746722","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746722","url":null,"abstract":"With increased social governance awareness on the usage of halogen products, studies on halogen free (HF) products as replacements are now becoming highly important among semiconductor industry players as well as researchers. In this study, IMC morphology of SAC305 on NiP substrate was used to study or compare the performance for different HF fluxes and halogenated flux candidates. On top of this, the activator used within the flux candidates is also being identified in order to understand the impact on fluxing capability towards the oxides layer removal. The study was focussed on wetting performance of the SAC305 interacting with different fluxes candidates on NiP substrate was on the impact to solder joint strength. Ball shear test and ball pull test were conducted to validate the strength of solder joint developed through the use of various fluxes. In summary, the selected water soluble HF flux provides good solder joint in general than the other HF flux candidates. Comparing IMC morphology among all flux candidates, it is concluded that high angle within IMC layers plays an essential role in ensuring good solder joint as well as the contribution of scallope shape IMC and the present of small Ag3Sn along IMC layer in solder joint strengthening.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115807499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Plasma process considerations in emerging semiconductor packaging technologies 新兴半导体封装技术中的等离子体工艺考虑
J. Getty, D. Chir
{"title":"Plasma process considerations in emerging semiconductor packaging technologies","authors":"J. Getty, D. Chir","doi":"10.1109/IEMT.2010.5746732","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746732","url":null,"abstract":"Plasma cleaning technology is a well known method of contamination removal and surface activation to enhance the performance and reliability of advanced semiconductor packages. It has also gained widespread acceptance and implementation over the last 10 years. With the continued introduction of new packaging technologies and materials, the applications for plasma technology have also broadened. This paper will review the considerations and performance benefits of employing plasma technology in flip chip, copper wirebonding and LED lens molding applications. The importance of using the optimum combination of process parameters and plasma technology in conjunction with different combination of materials will be the key underlying theme. This will be clearly illustrated firstly with a flip chip application example where the correct gas chemistry is shown to be important in achieving the desired adhesion and reliability characteristics in a flip chip underfill process. Quantitative data obtained from field studies will also be presented to show how plasma treatment can enable the realization of the low-cost benefits of copper wirebonding. Also discussed will be how the advantages of inline type plasma over a batch type system can produce significantly improved wirebond results. Finally, we will discuss how the adhesion promotion ability of plasma treatment enables the high-volume, low cost production of molded silicone LED lenses.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"49 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132709234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Package crack resolution through low stress dambar punch design: A six sigma DMAIC approach 通过低应力损伤冲床设计解决包装裂纹:六西格玛DMAIC方法
Angelo R. Uy, M. Picardal, Patrocinio Enriquez, Arnold C. Alaraz
{"title":"Package crack resolution through low stress dambar punch design: A six sigma DMAIC approach","authors":"Angelo R. Uy, M. Picardal, Patrocinio Enriquez, Arnold C. Alaraz","doi":"10.1109/IEMT.2010.5746729","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746729","url":null,"abstract":"Package micro-crack has been a stern problem in ON Semiconductors Philippines Inc (OSPI) Trim and Form (T&F) process. That despite numerous studies to eliminate the problem it still persist. Package micro-crack was of concern as it has a high chance to escape assembly inspection control and electrical test. And potentially will contribute to the product failure upon application of stress.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134361724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Evolutionary development of wafer level packaging 晶圆级封装的进化发展
J. Hunt
{"title":"Evolutionary development of wafer level packaging","authors":"J. Hunt","doi":"10.1109/IEMT.2010.5746740","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746740","url":null,"abstract":"IBM created the wafer processing technology and concepts more than 45 years ago that would later enable what we call Wafer Level Packaging. With its introduction of the Controlled Collapse Chip Connect (C4) solder bumping process for use in its Solid Logic Technology package, it paved the way for the larger solder bump technology that enabled die to be mounted directly on circuit boards using standard surface mount equipment, and standard pitch circuit board technologies. Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) came into volume production, with all of the “packaging” done while still in wafer form. It began slowly, with very small packages having solderball counts of 2–6 I/Os. Over the years, the production volumes have grown, and so has the I/O count. Much of the industry still perceives WLCSPs as limited to low I/O count simple applications. However, within the last few years, there have been growing demands for WLCSP packages with I/O counts of 300 and greater, and with higher levels of complexity.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131492811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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