三维积分叠加中衬底耦合效应的频域和时域表征

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI:10.1109/IEMT.2010.5746730

E. Eid, T. Lacrevaz, C. Bermond, S. Capraro, J. Roullard, B. Fléchet, L. Cadix, A. Farcy, P. Ancey, F. Calmon, O. Valorge, P. Leduc

{"title":"三维积分叠加中衬底耦合效应的频域和时域表征","authors":"E. Eid, T. Lacrevaz, C. Bermond, S. Capraro, J. Roullard, B. Fléchet, L. Cadix, A. Farcy, P. Ancey, F. Calmon, O. Valorge, P. Leduc","doi":"10.1109/IEMT.2010.5746730","DOIUrl":null,"url":null,"abstract":"In new circuits performed with 3D integration technology, electromagnetic interference through stacked silicon substrates may occur due to signals propagated in Through Silicon Vias (TSV) and along Redistribution Layers (RDL) [1]. So, to optimize electrical performances of these new 3D digital or RF circuits, substrate coupling effects need to be characterized, modeled and quantified in a large frequency bandwidth.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Frequency and time domain characterization of substrate coupling effects in 3D integration stack\",\"authors\":\"E. Eid, T. Lacrevaz, C. Bermond, S. Capraro, J. Roullard, B. Fléchet, L. Cadix, A. Farcy, P. Ancey, F. Calmon, O. Valorge, P. Leduc\",\"doi\":\"10.1109/IEMT.2010.5746730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In new circuits performed with 3D integration technology, electromagnetic interference through stacked silicon substrates may occur due to signals propagated in Through Silicon Vias (TSV) and along Redistribution Layers (RDL) [1]. So, to optimize electrical performances of these new 3D digital or RF circuits, substrate coupling effects need to be characterized, modeled and quantified in a large frequency bandwidth.\",\"PeriodicalId\":133127,\"journal\":{\"name\":\"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)\",\"volume\":\"129 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.2010.5746730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.2010.5746730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

在采用3D集成技术的新型电路中，由于信号在through silicon Vias (TSV)和Redistribution Layers (RDL)中传播，可能会产生通过堆叠硅衬底的电磁干扰[1]。因此，为了优化这些新型3D数字或射频电路的电气性能，需要在大频率带宽下对衬底耦合效应进行表征、建模和量化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Frequency and time domain characterization of substrate coupling effects in 3D integration stack

In new circuits performed with 3D integration technology, electromagnetic interference through stacked silicon substrates may occur due to signals propagated in Through Silicon Vias (TSV) and along Redistribution Layers (RDL) [1]. So, to optimize electrical performances of these new 3D digital or RF circuits, substrate coupling effects need to be characterized, modeled and quantified in a large frequency bandwidth.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)

自引率

0.00%

发文量