2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献

{"title":"Comparison of energy harvesting power management techniques and application","authors":"Mohd Sofwan Mohd Resali, H. Salleh","doi":"10.1109/IEMT.2010.5746768","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746768","url":null,"abstract":"There has been a significant increase in the research on energy harvesting device for low power applications in recreant years. This is due to smaller electronics power applications such as wireless and mobile electronics and the demand for better lifespan of batteries. One of the challenges of the harvesting energy from ambient is to convert, transfer and store the usable power effectively. In this context, there is a need to understand and design and efficient energy harvesting power management circuitry. In view of the issues, this paper compares several energy harvesting power management techniques and applications. Based on the comparison, suggestion on the design improvement are also included. This paper proposed improvement on the adaptive circuit as to get better efficiency. This paper will propose by using full bridge AC-DC rectifier to convert AC input voltage to usable DC voltage. In order to reduce power consumption of the circuit and power losses, comparator circuit is implementing as an adaptive approach to the DC-DC step-down converter. Simulation results are presented that output voltage from power management energy harvesting circuit is 3.0V with output power is 30mW. The efficiency reported as 80%. The total power losses are 7.5mW. Lastly this design presents a stand-alone system, single supply voltage and compatibility for micro-scale circuit integration.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126387488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra low CTE (0 PPM/C) polyimide film and its potential application","authors":"Y. Tsukada","doi":"10.1109/IEMT.2010.5746756","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746756","url":null,"abstract":"A CTE gap between a silicon chip and a package substrate is one of the most critical issues in securing reliability for a high-density packaging. We succeeded in a development of a new thermally stable and ultra low CTE polyimide film . The CTE is lower than that of silicon in a wide temperature range. A thick laminate sheet, with the thickness of 250 to 500 micrometers, composed with this ultra low CTE polyimide films shows low CTE as well. Since the sheet can be easily processed by machine cutting or laser drilling with a high aspect ratio, it is highly expected to perform as a core material for a thermally- reliable package substrate. Along with the role of core material, this polyimide film is able to be applied as a dielectric material for wiring layers as well. This paper describes possible applications of this film in a package substrate with early test data of thermal cycle stress.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The challenges of high density wires in C45SOI 40µm package","authors":"L. B. Yew, S. C. Teck","doi":"10.1109/IEMT.2010.5746743","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746743","url":null,"abstract":"For wirebonded IC package, the industry has moved from conventional ∼70um die pad pitch to ∼40um pad pitch for better device and cost performance. In addition to the finer pitch challenge, thinner wires have also been introduced. These process advances have led to wire shorting and wire sweep being critical in package reliability and production yield. In this study, a DOE was designed to evaluate various factors such as wire diameter, wire length, wire gaps and layout, and mold transfer speed effect on wire sweep. The test vehicle used is a 31×31mm2 Thermally Enhanced PBGA version II (TePBGA II). The main response monitored was wire sweep %. As it turned out. the results compiled showed that wire diameter is the dominant factor affecting wire sweep.. In order to continue to be able to use the thinner wires, the other secondary factors such as the wire length need to be reduced and wire layout to be optimized. The main portion of this paper describes the evaluation accomplished in minimizing wire sweep while allowing the use of thinner wires.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129556061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Keep on shrinking interconnect size: Is it still the best solution?","authors":"Denis Deschacht, S. D. Rivaz, Alexis Farcy, Thierry Lacrevaz, Bernard, Flechet","doi":"10.1109/IEMT.2010.5746734","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746734","url":null,"abstract":"According to the evolution between each new technological generation of CMOS ICs, ITRS suggests a reduction in interconnect sizes by a factor of around square root of 2. In this paper a reference design rule is based on a perfectly controlled technology of the CMOS 45 nm node, with interconnects width equal to their separation space. Our works are focused on the impact on signal transmission speed and delay along interconnects of decreasing the space or width. To avoid new industrial manufacturing constraints on cost and reliability, this study is performed without modifying process and materials used in the BEOL of CMOS 45 nm IC. We will study interconnects of 50 nm width, with a 50 nm space between lines in accordance with CMOS 32 nm FEOL requirements. In the second time we will relax geometrical constraints to enlarge the scope of application.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130752209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of pickling and mechanical surface treatment methods on adhesion strength of Ti oxide layer formed on Titanium alloy substrate","authors":"S. Izman, M. R. Abdul-Kadir, M. Anwar, E. M. Nazim, E. K. Khor, M. Konneh","doi":"10.1109/IEMT.2010.5746719","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746719","url":null,"abstract":"Titanium alloys are commonly used in biomedical application in hard tissues replacement especially for knee and hip implants but facing huge wear debris due to continuous cyclic contact within the joints of the implants. Diamond coating is a potential solution for improving the tribological and wear properties of the implants made from this alloy. Diamond is known for having high wear resistance property and chemical vapour deposition (CVD) is one of the most promising methods for diamond coating. However, the major concern for CVD process is the poor adhesion of the diamond to the substrate material due to the large mismatch of coefficient of thermal expansion (CTE) properties between the two. A suitable interlayer material can be introduced to reduce the gap of CTE differences by oxidation process. In this study, the effect of pickling temperature and mechanical surface treatment methods on the adhesion strength of Ti oxide interlayer prior to diamond coating were investigated. Besides, the thickness of oxide layer and surface morphology were also evaluated. Experiments were carried out on Ti6Al4V substrate by varying the surface treatment pickling temperature from 25°C to 50°C. In mechanical surface treatment, all samples were ground using #220 to #1200 grits and followed with polishing using alumina paste. After the surface treatment process, all the substrates underwent thermal oxidation for 25 hours at 900°C. The results showed that the adhesion strength of oxide layer increases with the increasing of pickling temperature. Mechanical surface pretreatment provides better adhesion of oxide layer than chemical pretreatment (pickling process). However, the adhesion strength decreases with the increases of oxide layer thickness.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116329286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correlation effects of ATE transfers: An empirical study","authors":"M. Marcos, Imee Rose M. Tagaca","doi":"10.1109/IEMT.2010.5746683","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746683","url":null,"abstract":"This study presents an empirical analysis of the effects on correlation of the site-to-site transport of ATEs. Four correlation scenarios are presented with permutations of calibration/non-calibration of the testers. The results show that the least number of uncorrelated tests are encountered when there is calibration at the reference tester site, with or without calibration on the target site. Also, there is no significant shift in the distribution of tests after the physical transport and the calibration of the testers. Any shift encountered in these cases can be attributed to a number of factors, such as device-specific sensitivity, vulnerability of related tester resources, or degradation of the representative units used per device. Overall, this study demonstrates that non-calibration at the target site, provided there is calibration at the reference tester site, is a viable and credible option for a less time-consuming and more cost-efficient correlation procedure, especially in massive transfer of ATEs.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126366485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Meeting the assembly challenges in new semiconductor packaging trend","authors":"Lim Lay Yeap","doi":"10.1109/IEMT.2010.5746731","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746731","url":null,"abstract":"Semiconductor packaging is being driven by the market requirement for an increase in operating speed and higher functional density, which requires chip makers to develop more sophisticated packaging to meet this trend. On the other hand, there are demands for the package to be smaller, thinner and less expensive, imposing tremendous challenges on chip manufacturers to meet compelling assembly to meet assembly challenges in this new packaging technology. As technology grows, the demand for new packages with even greater sophistication will drive package innovation. The purpose of this paper is to describe the potential challenges that encounter during assembly process, material selection and characterization in order to manufacture a product that has a low profile, high functionality, and low cost, green and reliable package for molded leadless packages. The challenges will include assembling the molded lead less package with multiple types of epoxy, wires and chip and at the same time shrinking the total package dimensions in order to meet the market requirement. Selection of material both direct and indirect material are also crucial. Any material CTE mismatches makes moisture performance more difficult to achieve.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126519692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cu wire neck fatigue fracturing elimination","authors":"Song Xiaoqing, Wei Haili, Z. Hong-bin","doi":"10.1109/IEMT.2010.5746752","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746752","url":null,"abstract":"This paper present the challenges of elimination on Cu wire neck fatigue fracturing issue after TC (Temperature Cycle) and IOL (Intermittent Operational Life Test). The qualification lots were detected fracturing after TC1000 cycles and IOL15000 cycles due to stress inner of package; after detail analyze the cross section samples, there is no any abnormal was found from fresh unit; but the minor cracks were detected along the grain edge of Cu crystalloid from TC/IOL units. A big challenge is to search out the key factors which are for fatigue fracturing. As presented in this paper, the Wire Looping Length, Looping Type, Loop Reversion Data, Free Air Ball Size, Wire Type, Wire Grain Size, Capillary Tip Angle, Compound Moisture, Curve Time and TC Profile were considered, DOE result indicate Tg & CTE of compound, package type and TC profile is Key factors for fracturing.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128990892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Molding technology development of large QFN packages","authors":"JW Seah, Sw Wang","doi":"10.1109/IEMT.2010.5746720","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746720","url":null,"abstract":"Encapsulation of large QFN packages (> 5 × 5mm) are quite challenging as compared to normal small QFN packages as the big die pad in leadframe and multiple narrow gaps between leads may caused mold void rejects at the half etch areas. High density of fragile wires is prone to have wire sweep too as the EMC flow impact on longer wire length is significant which can caused wires sweep during mold filling.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130392930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cooling performance of piezoelectric fan in notebook system","authors":"Ng Kar Mun, I. Sauciuc, Hiroaki Wada, N. Tanaka","doi":"10.1109/IEMT.2010.5746707","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746707","url":null,"abstract":"Thin form factor and high computing performance are the inevitable trend of notebook industry. Both vectors impose more stringent challenge on thermal solution design to maintain internal components and external chassis surfaces within temperature requirements. Cooling industry contributed great effort in miniaturizing conventional blower fan to thin form factor for supporting thin notebook cooling. However, due to the physical size constraints such as rotary blade, magnetic coil, bearing mechanism & circuit board, the effective flowrate of thin form factor fan is relative low. Multiple past researches have been focusing on characterization of thermal performance at component level. However, investigation of practical cooling application of piezofan in thin notebook has not been widely studied. This paper investigates the feasibility of implementing piezoelectric fan (referred as piezofan from now) as an alternative cooling technology in thin notebook. The piezofan design is constrained by volumetric size not greater than blower fan used for cooling thin notebook. The selected notebook is low power thin & light 13″ notebook, with processor TDP (Thermal Design Power) of 18W. Firstly, the cooling impact of heat exchanger design is studied in terms of position, fin gap & inlet shape. The optimum cooling performance is observed when heat exchanger design is with 1.5mm fin gap, additional recesses at top & bottom of inlet plane and positioned at in front (∼0mm) of piezofan vibration tip. Secondly, cooling characteristic of piezofan is studied in terms of blade length (l), thickness (t), operating frequency (ƒ) and amplitude (A). First resonance frequency is observed to be linearly dependent on t/l2. The cooling performance of piezofan is concluded inversely power to A׃. Better cooling performance is obtained at higher resonance frequency and larger vibration amplitude. Piezofan with shorter vibration blade generates higher A׃ value (better cooling performance). The sound pressure level of piezofans are measured as well, and found to be below typical notebook acoustic limit of 40dB(A). It is observed that higher resonance frequency generates higher acoustic in general. Finally, a piezofan operating at 138Hz frequency and 30Vpp voltage is installed in selected thin & light notebook system for thermal test. The temperature of processor, palm rest, touch pad and bottom skin of notebook are monitored. Test data indicated that piezofan perform better cooling for processor and bottom skin when compared with blower fan. Other components are less than 10% temperature difference. This data shows the thermal feasibility of piezofan to be implemented in thin & light notebook with processor TDP of 18W (or other low power mobile devices), with low acoustic noise and low power consumption.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132964752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}