2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献_第4页

Apply to the package substrate of low low-CTE polyimide laminate sheet 适用于低cte聚酰亚胺层压板的封装基板

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746736

Toshiyuki Tsuchiya, Takefumi Yoshida, M. Tsutsumi, S. Maeda, Y. Tsukada

引用次数: 0

Ultra low loop conversion from gold to copper wire 从金线到铜线的超低回路转换

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746666

Lee Kuan Fang, O. Kwon, O. Yauw, D. Capistrano, B. Milton

引用次数: 4

Package warpage challenges for LQFP 144 lead CMOS 90 device and it's impact to lead coplanarity LQFP 144引脚CMOS 90器件的封装翘曲挑战及其对引脚共面性的影响

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746703

Teng Seng Kiong, I. Ruzaini, Kesvakumar, Foong Chee Seng

{"title":"Package warpage challenges for LQFP 144 lead CMOS 90 device and it's impact to lead coplanarity","authors":"Teng Seng Kiong, I. Ruzaini, Kesvakumar, Foong Chee Seng","doi":"10.1109/IEMT.2010.5746703","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746703","url":null,"abstract":"Package warpage or generally referred to as plastic package deformation has become more challenging with larger and thinner package body sizes. The detrimental effects of the package warpage are more prominent in peripheral packages with leads such as fine pitch LQFP (Low Profile Quad Flat Package). As all the leads are embedded in the plastic body, the warpage will displace the leads in the same direction of the warp after the trim and form step. In the first half of the paper, we characterized the warpage of different LQFP packages designs using Akrometrix Thermoire. It was found that larger die size and smaller down set are favorable to reducing package warpage. In the second half of this paper, we explored various factors such as molding process parameters, post mold cure conditions, effects of direct materials properties, and package geometry to determine their impact on the package warpage and lead coplanarity for the LQFP molded package. Molding parameters such as cure time and molding temperature were evaluated in a series of DOEs in attempts to find the most promising factors that can control the warpage. Similar DOEs were also carried out in the post mold cure process coupled with various methods of clamping. As for the direct materials, studies focusing on molding compound properties such as coefficient of thermal expansion (CTE), higher filler content, higher glass transition temperature Tg, and lower mold shrinkage factor have been completed as well. From these series of analyses and experiments, we understood how the leads formed with spring back effect in a warped package will end up with poor coplanarity measures. It is also found that the combination of several material properties that are not optimal will further deteriorate warpage and cause poor lead coplanarity. These findings and results will be shared in this paper and recommendations to correct the issue are presented.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimization of an isotropic etching process on silicon wafers 硅片各向同性蚀刻工艺的优化

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746677

R. Dolah, H. Musa

{"title":"Optimization of an isotropic etching process on silicon wafers","authors":"R. Dolah, H. Musa","doi":"10.1109/IEMT.2010.5746677","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746677","url":null,"abstract":"Etching process involves various chemical reactions and reflects significantly on silicon wafer quality. Etching parameters are evaluated in order to optimize the isotropic etching process. For optimization purpose, Design of Experiment (DOE) with full factorial design is employed. Etching factors namely the bubbling flow rate, wafer rotation, and etchant temperature are randomised with additional three centre points to observe any curvature. The responses studied are etching removal, total thickness variation (TTV) and wafer brightness. It is found that etchant temperature gives major impact on all three responses stated above. The etchant temperature is the main effect factor and significantly affects TTV. Additionally, the etchant temperature and bubbling flow rate provide interaction effects on both the etching removal and wafer brightness. A higher bubbling flow rate is required to ensure etching removal and brightness within specification. Besides studying these three responses, the wafer surface after etching is additionally analysed using ADE Infotool software which captures the etched profile and its thickness. The ADE result indicates that a higher temperature contributes to a more concave shape of etched wafer, thus resulting in higher TTV and sending the wafers out of specification. Finally, the optimum condition is tested on a final run. The removal uniformity is observed in removal distribution graphs. The etching performance is enhanced with the optimized value of bubbling flow rate, etchant temperature and wafer rotation to achieve the best removal distribution.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127338401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

State-of-the-art and trends in 3D IC/Si integrations and WLP 3D IC/Si集成和WLP的最新技术和趋势

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746774

J. Lau

引用次数: 3

Power gating techniques on Platform Controller Hub 平台控制器集线器的电源门控技术

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746728

F. Tan, S. G. Pang, L. K. Yong, Chee Siong Lee

{"title":"Power gating techniques on Platform Controller Hub","authors":"F. Tan, S. G. Pang, L. K. Yong, Chee Siong Lee","doi":"10.1109/IEMT.2010.5746728","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746728","url":null,"abstract":"Energy efficiency has long been a first-order goal for mobile devices such as cell phones to extend battery life. In the last decade, effective energy use has also become a focus for larger computing devices for several reasons; namely expansion of mobile computing and data centers. Customers require maximum battery life from notebooks, netbooks, and tablets. Achieving optimal battery performance requires careful management of energy consumption. This paper describes the power gating techniques which has achieved ∼1000mW of effective power savings on Platform Controller Hub (PCH) and is proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, to make power savings possible without performance trade-off, many design considerations combining architecture, floorplanning, innovative hardware design and software configurations are required. This paper presents the power gating strategies starting from early design planning to post silicon validation correlation methodology considering: 1) silicon floorplan partitioning into multiple power domains 2) stages of PFET switches assignment 3) The trade-off between a wake-up overhead and leakage savings design 4) the complete definition of power gate/ungate power sequence from partition level to system level 5) PDN noise analysis and leveraging of “zero-cost” noise mitigation techniques to address the various possible worst case power noise droop events cause by power gate/ungate activities. These power gating strategies are consider successful, when not only the desired power target is achieved; but a smooth transition of power state from sleep mode to full power mode and vice versa, is achieved without system hang or performance corruption. The paper is concluded with post silicon validation results correlated to selected individual power partition's gate/ungate activity; which is controlled by a specially customized test script to examine the power fet's gating/ungating functionality v.s. design expectation.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The correlation of package coplanarity and reflow warpage to SMT 封装共面性和回流翘曲与SMT的关系

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746680

Yung Hsiang Lee, K. Ong, W. K. Loh, Shaw Fong Wong, P. Gill, Kah Kee Tan

引用次数: 5

Alternative robust reliability solution for silver finishing 可选的可靠解决方案的银整理

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746708

S. Goh, S. Lee, Din-Ghee Neoh, Sia-Wing Kok

引用次数: 0

Investigation of bond pad etching chemistries for passivation crack 钝化裂纹粘结垫腐蚀化学研究

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746662

Rusli Ibrahim, M. Leoni, Au Yin Kheng, Poh Zi Song Kenny, P. Eu

{"title":"Investigation of bond pad etching chemistries for passivation crack","authors":"Rusli Ibrahim, M. Leoni, Au Yin Kheng, Poh Zi Song Kenny, P. Eu","doi":"10.1109/IEMT.2010.5746662","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746662","url":null,"abstract":"Wire bonding is still a very common method for connecting the pads on a chip to the package. During the ultrasonic wire bonding process, several failures such as ball neck failure, missing ball, bond metal peeling or crack etc., may be generated. Of those failures, bond pad peeling or crack is a phenomenon detected after bonding process and is identified as a critical reliability problem and is known as a complex defect to investigate. Bond pad cracks pose a high reliability risk and potential failure during environmental stress testing. Damage to the bond pad may be the result of sub optimized probe or wirebond process parameters, as well as poor pad design. In addition, bond pad cracks may be unintentionally induced by the cratering test chemical etch solution. There is a case where an assembly folk reported had a bond pad crack, but none of the parts have failure during electrical test or even after reliability stress. In such case, we believe the crack found at assembly was an artifact induced by etching chemical, resulting the over-rejecting the parts. This paper specifically discusses a comparative analysis of various bond pad etching methods and their impact on bond pad cracking. There are few interesting findings will also be shared during the discussions. Failure analysis results are also briefly discussed.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130663986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Adaptation of brass core lead frame material in IC packaging 铜芯引线框架材料在集成电路封装中的应用

2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT) Pub Date : 2010-11-01 DOI: 10.1109/IEMT.2010.5746710

Koo Kok Kiat, T. Min

引用次数: 1