2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)最新文献

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Advanced copper wire bonding technology 先进的铜线粘接技术
H. Ho
{"title":"Advanced copper wire bonding technology","authors":"H. Ho","doi":"10.1109/IEMT.2010.5746772","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746772","url":null,"abstract":"Wire bonding is the most dominant form of first-level chip interconnects in microelectronics with gold wire bonding taking the lead for the past few decades. Today, it is evident that the shift from gold to copper wire bonding is genuinely picking up, due to both a surge in gold prices and recent developments in copper wire bonding technology. The course will be divided into two main sections:-1. The first section would discuss the technology trends, the building blocks for copper wire bonding, the key process factors to achieve a reliable copper wire bond and what are the implementation challenges with downstream processes such as interaction with mold compound and its package reliability aspects. 2. The second section would discuss the recent developments in equipment, copper wire material and capillary and how these help realize copper wire bonding in production implementation and how the gaps between gold and copper wire bonding are shorten.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132068808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Proposed approach in applying optical character recognition for thermal image processing 一种光学字符识别在热图像处理中的应用方法
C. Ti, Sim Kok Swee, T. C. Ping
{"title":"A Proposed approach in applying optical character recognition for thermal image processing","authors":"C. Ti, Sim Kok Swee, T. C. Ping","doi":"10.1109/IEMT.2010.5746767","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746767","url":null,"abstract":"This conference paper concerns the application of optical character recognition in the processing of thermal images. Thermal images that lack colour index metadata are subjected to a custom-made program, which performs the aforementioned tasks. The temperature values corresponding to the color intensities of every pixel in an image can be determined without the need to manually input details of the temperature scale of the said image. The program is useful for automating the processing of large batches of thermal images of uniform format and size as typically used in industrial preventive maintenance.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130122323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Concurrent design for robust and cost efficient semiconductor manufacturing 并行设计稳健和低成本的半导体制造
F. Y. Lee, Lim Siew Lin, W. Yong
{"title":"Concurrent design for robust and cost efficient semiconductor manufacturing","authors":"F. Y. Lee, Lim Siew Lin, W. Yong","doi":"10.1109/IEMT.2010.5746717","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746717","url":null,"abstract":"Rapid development in the semiconductor industry requires close collaboration between the design and manufacturing teams in order to increase performance, reduce cost and improve the quality of the electronic products manufactured. The current development process is mainly chip-driven design flow that regards package design as a small add-on. This paper proposes the concurrent design concept of chip and package to fully exploit concurrent design benefits to overall product life cycle performance. Successful deployment of the concurrent design concept allows both the chip and package designers from different geographical locations to incorporate the best design attributes into the semiconductor products. This ensures both product quality and reliability requirement are achieved. The concurrent design concept is further expanded by the introduction of group technology approach into lead frame design for better cost management.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131926239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Influence of wafer probing against initial bonding 晶圆探测对初始键合的影响
Suresh Kumar, Siva Rao, Tan Kim Guan, F. Harun
{"title":"Influence of wafer probing against initial bonding","authors":"Suresh Kumar, Siva Rao, Tan Kim Guan, F. Harun","doi":"10.1109/IEMT.2010.5746671","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746671","url":null,"abstract":"Wafer probing technology is a critical testing technology used in the semiconductor manufacturing and packaging process. A well-designed probing system must enable low and stable contact resistance when each needle-like probe makes contact with the IC chip-bonding pad. During wafer testing, probe needles are brought in mechanical contact with aluminum bond pads and electrical contact is made as the probes “scrub” through the oxide and contaminants on the pad surface. This scrubbing action causes the probe needle to disturb or damage the pad metal. This scrub damage can adversely impact the wire bond quality at assembly and add extra costs by lowering bond and assembly yields. As the amount of pad damage increases, the strength and integrity of the bond is reduced. If the bond is too weak, the ball could potentially lift off the pad during the bond process at assembly. This effect is exacerbated for ultra fine pitch bond pads since a larger percentage of the total pad area is damaged during probe test. This paper will be evaluating on the different impacts of probe conditions to wire bond-ability based on both the probe and wafer technology. It was found that pad damage area has a direct impact to bond quality. The larger pad damage area the lower the bond quality and this depends on the factors like probe technology, number of probe touchdown, probe overdrive as well as optimal wire bonding parameters. Results showing that vertical probe technology are better than both advanced and standard cantilever technology while bonding quality can still be maintained even if the probe damage is large as long as bond location is at the toe and not at the center or the heel of the damage area.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132051108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Metal line and via electromigration improvement with wafer level tests 金属线和通过电迁移改进与晶圆级测试
N. H. Seng, Ecole Hei, R. Tan
{"title":"Metal line and via electromigration improvement with wafer level tests","authors":"N. H. Seng, Ecole Hei, R. Tan","doi":"10.1109/IEMT.2010.5746673","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746673","url":null,"abstract":"In semiconductor, the reliability of interconnects is assessed through electromigration (EM) on specially-designed metal line and via test structures. There are different types of test structures and methodologies for qualification and process monitoring purposes. Packaged level constant current EM (PLR EM) test is a widely accepted method for technology qualification. Wafer level accelerated tests such as Standard Wafer Electromigration Accelerated Test (SWEAT) and Isothermal method (ISOT) are also used to assess the metallization system. However, these methods are normally limited to monitoring and tool comparison when process is stable with enormous baseline data. This paper demonstrates the use of SWEAT and ISOT for process improvement. During technology developments, bimodal behavior of EM lifetime distribution was observed for via test structures. In order to optimize the time spent for testing and cost as well as to solve the PLR EM limited test capacity constraint, the SWEAT and ISOT tests were selected to identify the areas of improvement. These methods have successfully shortened the problem solving process and reduced the expensive long PLR EM test. The EM lifetime has been improved by changing the barrier metal and via glue processes.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128729307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Separation of the bar: Systemic solution of runner bar cull remain problem through leadframe design change 棒料分离:通过引线框架设计变更,系统解决了流道棒料残留问题
R. Tan, Jose Mario Gemal, L. Lim
{"title":"Separation of the bar: Systemic solution of runner bar cull remain problem through leadframe design change","authors":"R. Tan, Jose Mario Gemal, L. Lim","doi":"10.1109/IEMT.2010.5746701","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746701","url":null,"abstract":"With the drive to enhance Moisture Sensitivity Level for TSSOP-48L package in OSPI, plating type for this package was converted to roughened treated upgraded Pre-Plated Nickel Palladium Gold(RT-UPG PPF). The enhanced property of this plating type to adhere to the epoxy molding compound, results in processing difficulty for the runner bars to be removed from the strip. This paper will discuss in detail the systematic approach taken to resolve the problem, the design changes implemented both on the material and the tool parts. It closes on the point that with the new leadframe design a more robust process is achieved without compromising the integrity of the package and processes involved.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129359018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low profile tsop approach for MSL 1 delamination free 低轮廓tsop方法MSL 1无分层
C. Lum
{"title":"Low profile tsop approach for MSL 1 delamination free","authors":"C. Lum","doi":"10.1109/IEMT.2010.5746674","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746674","url":null,"abstract":"A low profile TSOP package has the history of die paddle and lead post delamination after pre-con MSL 1 reflow 260°C.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of Ni metallization on interfacial reactions and die attach properties of Zn-Al-Mg-Ga high temperature lead-free solder Ni金属化对Zn-Al-Mg-Ga高温无铅焊料界面反应及模具附着性能的影响
A. Haque, Y. Won, B. Lim, A.S.M.A. Haseeb, H. Masjuki
{"title":"Effect of Ni metallization on interfacial reactions and die attach properties of Zn-Al-Mg-Ga high temperature lead-free solder","authors":"A. Haque, Y. Won, B. Lim, A.S.M.A. Haseeb, H. Masjuki","doi":"10.1109/IEMT.2010.5746721","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746721","url":null,"abstract":"Interfacial reactions during Si die attachment with Zn-Al-Mg-Ga high-temperature lead (Pb)-free solder on bare Cu lead-frame (Tamac 4) and Ni metallized Cu lead-frame were investigated using an optical microscope, scanning electron microscope (SEM) and energy dispersive x-ray (EDX). Die attachment was performed in an automatic die attach machine in a forming gas environment at temperature 380°C. The back side of the die was metallized with Ti/Ni/Ag layers. Comparative studies of die attach properties such as wetting, void and die shear strength on bare and Ni metallized Cu lead-frame was made. Cross sectional microstructural investigation revealed that as many as three intermetallic compound (IMCs) layers form at the solder/lead-frame interface for bare Cu lead-frame. A CuZn intermetallic layer forms close to copper, a scallop shaped CuZn4 forms at the solder side, while Cu5Zn8 forms at the middle. At the interface with Si die, IMC layer could not be detected by SEM. With Ni metallized Cu lead-frame, no IMC layer was observed at the solder/lead-frame as well as Si die/solder interface by SEM. Wetting on Ni metallized Cu lead-frame was found to be lower as compared to that at bare Cu lead-frame. Die shear strength was found to be higher on bare Cu lead-frame (24.2 MPa) as compared to Ni metallized Cu lead-frame (20.5 MPa). Die shear strength of standard Pb-5Sn solder was also measured for comparison and found to be 28.2 MPa.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124159557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A LEAN approach in processor platform validation (PPV) effective test interface unit (TIU) performance improvement 精益方法在处理器平台验证(PPV)中的有效改进测试接口单元(TIU)的性能
Chia Saw Ean, Choo Pak Kee
{"title":"A LEAN approach in processor platform validation (PPV) effective test interface unit (TIU) performance improvement","authors":"Chia Saw Ean, Choo Pak Kee","doi":"10.1109/IEMT.2010.5746770","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746770","url":null,"abstract":"This paper describes the innovation & creativity with LEAN approach for PPV TIU performance improvement. PPV is CPU's platform validation product screening to confirm product functionality in actual customer computer systems running MS Windows, Linux or other operating systems and software, Test Interface Unit (TIU) is type of custom interface for product testing based on customer requirement. While LEAN is the relentless pursuit of adding value for the customer, waste elimination, and continuous improvement from a standard at the point of activity by everyone, everywhere, everyday. The Intel house of LEAN systematically identifies the root cause(s) of problems in a business process and seeks to effectively eliminate them through an iterative approach to process improvement by 4 LEAN rules and 5 LEAN principles (Fig.1).","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127088576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interfacial reactions of SAC305 and SAC405 solders on electroless Ni(P)/immersion Au and electroless Ni(B)/immersion Au finishes SAC305和SAC405焊料在Ni(P)/ Au和Ni(B)/ Au表面的界面反应
S. Aisha, A. Ourdjini, N. M. Wah, H. C. How, Y. T. Chin
{"title":"Interfacial reactions of SAC305 and SAC405 solders on electroless Ni(P)/immersion Au and electroless Ni(B)/immersion Au finishes","authors":"S. Aisha, A. Ourdjini, N. M. Wah, H. C. How, Y. T. Chin","doi":"10.1109/IEMT.2010.5746712","DOIUrl":"https://doi.org/10.1109/IEMT.2010.5746712","url":null,"abstract":"The formation of intermetallic compounds (IMCs) on solder pads is strongly affected by the type of PCB surface finish since different finishes may lead to several different interfacial reactions and IMCs formation. Since the joint reliability is also determined by the type of the interfacial IMC layer between the solder and substrate, understanding how such intermetallic compounds form and grow during soldering and subsequent thermal ageing is essential. In this paper, experimental results of the effect of three different surface finishes namely: electroless nickel (phosphorus)/immersion gold, electroless nickel (boron)/ immersion gold and bare copper (for comparison) on the formation and growth of interfacial reactions during soldering and thermal ageing with Sn-3Ag-0.5Cu and Sn-4Ag-0.5Cu solders are presented. Several techniques of materials characterization including optical, image analysis, scanning electron microscopy and energy dispersive X-ray analysis were used to examine and quantify the intermetallics in terms of composition, thickness and morphology. The results showed that after soldering on Ni-Au finishes the reaction layer was found to consist of only one layer of (Cu, Ni)6Sn5 with a needle-shape morphology. In addition, the results from SEM with energy dispersive x-ray (EDX) have revealed that isothermal aging at 150°C has caused the thickening and coarsening of IMCs as well as changing them into more spherical shape. During soldering on Ni(B)/Au finish it was observed that closer control of the reflow temperature was very important compared to soldering on Ni(P)/Au finish. Selective etching of solder joints also revealed that the morphology of the intermetallic formed is different across a single solder joint from the centre to the outside edge.","PeriodicalId":133127,"journal":{"name":"2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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