Meeting the assembly challenges in new semiconductor packaging trend

Abstract

Semiconductor packaging is being driven by the market requirement for an increase in operating speed and higher functional density, which requires chip makers to develop more sophisticated packaging to meet this trend. On the other hand, there are demands for the package to be smaller, thinner and less expensive, imposing tremendous challenges on chip manufacturers to meet compelling assembly to meet assembly challenges in this new packaging technology. As technology grows, the demand for new packages with even greater sophistication will drive package innovation. The purpose of this paper is to describe the potential challenges that encounter during assembly process, material selection and characterization in order to manufacture a product that has a low profile, high functionality, and low cost, green and reliable package for molded leadless packages. The challenges will include assembling the molded lead less package with multiple types of epoxy, wires and chip and at the same time shrinking the total package dimensions in order to meet the market requirement. Selection of material both direct and indirect material are also crucial. Any material CTE mismatches makes moisture performance more difficult to achieve.