IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Aerosol-Jet Printed High-Q Quasi-Optical FSSs on Flex Substrates Using a Novel Parylene Lift-Off Process","authors":"Sambit Kumar Ghosh;Ethan Kepros;Premjeet Chahal","doi":"10.1109/TCPMT.2024.3521292","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3521292","url":null,"abstract":"This article introduces a new method to fabricate low-loss terahertz (THz) frequency-selective surfaces (FSSs) on flexible substrates. The process involves the printing of periodic metallic patterns on glass substrate using aerosol-jet printing (AJP) technology and silver-based nanoparticle ink followed by a novel lift-off process using thin parylene-C. The printed structures on glass can be sintered at high temperatures to achieve high conductivity silver structures. These printed structures are lifted of using a thin (<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m) parylene-C. Use of thin parylene-C reduces the effective dielectric losses. Several designs are demonstrated including parallel wire-grid and a tilted I-shaped polarizer, and a few THz FSS bandpass and band-stop filters. All the prototypes are designed, fabricated, and experimentally validated. The proposed FSSs can find applications in the next generation of low-loss THz flexible electronics.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"244-252"},"PeriodicalIF":2.3,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wideband Filtering and Circularly Polarized Antenna Arrays With Self-Packaged Multilayer Suspended Substrate Technique","authors":"Jia-Xing Guo;Jian-Kang Xiao;Tan Song","doi":"10.1109/TCPMT.2024.3519434","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3519434","url":null,"abstract":"In this article, a new butterfly-shaped filtering antenna array with Chebyshev filtering response, and a new wideband circularly polarized antenna array have been proposed, both using self-packaged multilayer suspended substrate technique. The filtering antenna array integrates the functions of a bandpass filter, a power divider, and a <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> antenna array by using multiple coupling resonators, while the circularly polarized antenna array is constructed by the wide slot structure using sequential rotation technique with 90° phase difference on neighboring antenna unit. Measured by vector network analyzer and spherical multiprobe test system, the filtering antenna array has been demonstrated with an impedance bandwidth of 11.8%, a favorable gain of 10.5 dBi, and a pair of gain zeros; meanwhile, the circularly polarized antenna array has a measured fractional impedance bandwidth of 60.9%, a maximum gain of 10.2 dBi, and a wide 3 dB axial ratio bandwidth covering 3.18–5.8 GHz. The measured results agree with the simulations. The proposed works integrate the advantages of suspended coplanar waveguide (SCPW), multiple resonators including microstrip patches and wide slots, which not only improve the design flexibility but also achieve wideband and favorable gain. While the feeding network and the radiation elements can be protected by the self-packaged construction.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"309-318"},"PeriodicalIF":2.3,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Millimeter-Wave On-Chip Ultrawideband Bandpass Filter on Coupled Line Based Bi-Path Topology Using GaAs Technology","authors":"Zhuowei Zhang;Gang Zhang;Kam-Weng Tam;Xin Zhou;Shichang Chen","doi":"10.1109/TCPMT.2024.3519369","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3519369","url":null,"abstract":"In this article, using gallium arsenide (GaAs) technology, a revolutionary millimeter-wave on-chip ultrawideband (UWB) bandpass filter (BPF) with greatly enhanced operation performance is demonstrated for the first time. By utilizing quarter wavelength short-circuited lines with an open-circuited interdigital coupled line and a short-circuited combine coupled line, it is altered from the traditional wideband BPF structure to create a flexible coupled line based bi-path topology. In comparison to the traditional structure, the suggested topology can efficiently increase passband selectivity with more flexible transmission zeros (TZs), as well as two more transmission poles (TPs) for a flatter UWB passband and a larger return loss (RL) bandwidth. For verification, an on-chip UWB BPF prototype using 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaAs pHEMT technology is designed, fabricated, and measured. The measurements show that it has a center frequency of 45.3 GHz with a fractional bandwidth (FBW) of 135%. A good agreement is found between the simulated and measured data.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"553-559"},"PeriodicalIF":2.3,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward TSV-Compatible Microfluidic Cooling for 3D ICs","authors":"Geyu Yan;Euichul Chung;Erik Masselink;Shane Oh;Muneeb Zia;Bharath Ramakrishnan;Vaidehi Oruganti;Husam Alissa;Christian Belady;Yunhyeok Im;Yogendra Joshi;Muhannad S. Bakir","doi":"10.1109/TCPMT.2024.3516653","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3516653","url":null,"abstract":"Cooling presents a significant challenge for high-performance 3-D integrated circuits (3D ICs). To this end, this research explores through-silicon via (TSV)-compatible micropin-fin heat sink (MPFHS) for high-power 3-D chip stacks. Copper TSVs with a diameter of <inline-formula> <tex-math>$5.2~mu $ </tex-math></inline-formula>m and a high aspect ratio (HAR) of 29:1 are developed. An extensive experimental and computational investigation of the MPFHS under varying flow rates and power conditions was conducted, showing that the MPFHS maintains an average chip temperature below <inline-formula> <tex-math>$72~^{circ }$ </tex-math></inline-formula>C, even with a total power dissipation of 500 W and a power density of 312 W/cm2 at a flow rate of 117 mL/min. The minimum total thermal resistance achieved was <inline-formula> <tex-math>$0.286~^{circ }$ </tex-math></inline-formula>C<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/W.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"104-112"},"PeriodicalIF":2.3,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Less Is More: Non-TIM Air-Cooled Ceramic Packaging for SiC Power Modules to Extend Thermal Performance and Mechanical Reliability Boundaries","authors":"Zhaobo Zhang;Xibo Yuan;Wenzhi Zhou;Mudan Chen;Elaheh Arjmand;Bohao Zhang;Wenbo Wang","doi":"10.1109/TCPMT.2024.3513944","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3513944","url":null,"abstract":"Power module packaging remains one of the constraints preventing silicon carbide (SiC) devices from realizing high power density and optimal reliability in converters. This article proposes a non-thermal interface material (TIM) air-cooled power module architecture, i.e., chip-on-heatsink, to enhance both thermal performance and structural reliability. The chip-on-heatsink packaging bonds conductive copper traces and an aluminum nitride (AlN) ceramic heatsink together without requiring TIM. This non-TIM packaging design streamlines the manufacturing process by eliminating certain steps, such as attaching the bottom copper layer on substrates and assembling heatsinks, since there are few layer stacks between chips and the heatsink. Two types of 1200 V, 36 A power modules are manufactured and experimentally compared. One utilizes the non-TIM structure integrated with <inline-formula> <tex-math>$50times 38times 24$ </tex-math></inline-formula> mm AlN ceramic heatsink, while the other follows the standard conventional packaging equipped with the same size 6063 Al Alloy heatsink. Tested under various air cooling and power loss conditions, the non-TIM power module consistently exhibits approximately a 2% reduction in junction-to-ambient thermal resistance compared to the traditional module, indicating the enhanced thermal performance of the non-TIM packaging. Furthermore, continuous performance testing confirms the suitability of the non-TIM power module packaging for operation at 650 V dc-link with 2 kW, making it a feasible choice for power converter applications. Moreover, an electro-thermal-mechanical finite element analysis (FEA) model and the digital image correlation (DIC) test are employed to evaluate the in-plane deformation. Results reveal that the maximum stress of the MOSFETs for the non-TIM packaging is significantly reduced by up to 40.2% along the defined path compared to the conventional structure, demonstrating the potential for better reliability with the proposed packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"512-524"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic IGBT Compact Thermal Network Model Over Long Time Scales","authors":"Mingyao Ma;Qian Zhang;Weisheng Guo;Qiwei Song","doi":"10.1109/TCPMT.2024.3513323","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3513323","url":null,"abstract":"The cause of failures in insulated gate bipolar transistor (IGBT) modules is primarily attributed to temperature-related factors. Accurately estimating the junction temperature of IGBT modules is crucial for enhancing their reliability. Currently, thermal network models stand as commonly used tools for estimating the junction temperature of IGBT modules. However, prevailing thermal models exhibit certain limitations in accurately predicting the junction temperature, particularly when considering the degradation of chip solder within IGBT modules. This article presents a practical degradation model of the chip solder layer, establishing a functional correlation between the chip solder degradation rate and the number of power cycles. A dynamic compact thermal network model over long time scales is established, and the method for thermal parameter extraction is discussed. The finite-element simulation and experimental results show that the dynamic compact thermal network model can accurately estimate the junction temperature.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"123-130"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2024.3500721","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500721","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C4-C4"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Noncontact Integration of Photonic IC and Electronic IC via Inductively Coupled Interconnects","authors":"Tongchuan Ma;Liyiming Yang;Yanlu Li;Yuan Du","doi":"10.1109/TCPMT.2024.3511042","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3511042","url":null,"abstract":"This letter presents an innovative noncontact packaging technique for photonic integrated circuits (PICs) and electronic integrated circuits (EICs) through inductively coupled interconnects. The primary aim of this approach is to enhance thermal isolation between the heat-generating electrical logic die and the thermally sensitive optical interferometer die. The feasibility of this contactless transceiver, which fulfills information transmission from the laser Doppler vibrometry (LDV) to the EIC, is substantiated via electromagnetic simulations. Furthermore, thermal simulations conducted by COMSOL prove that this packaging configuration could potentially reduce the temperature of PICs by up to <inline-formula> <tex-math>$4.6~^{circ }$ </tex-math></inline-formula>C when compared to the conventional 3-D stack packaging, underlining its potential for improved thermal performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"232-234"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142992901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2024.3500719","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500719","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778114","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2024.3500715","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500715","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778162","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}