IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"The Effect of Particle Pollution on the Temperature Rise of Assembled Printed Circuit Boards","authors":"Shengjie Liu;Hansheng Zhang;Fan Zhang;Yin Luo;Zhengyang Cui;Yilin Zhou","doi":"10.1109/TCPMT.2026.3666180","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3666180","url":null,"abstract":"During the long-term operation of electronic devices, airborne dust particles are carried by airflow into the interior of the equipment, where they deposit on the surfaces of printed circuit boards (PCBs) and their assembled electronic components. This deposition obstructs normal heat dissipation, thereby increasing the risk of component failure. To investigate the effect of dust accumulation on the temperature rise of PCBs with integrated electronic components, this study proposes an innovative thermal modeling approach by treating deposited dust as an equivalent porous medium film. Gradient-density quartz particle deposition experiments combined with image recognition techniques were employed to determine the porosity of the dust layer. Based on thermal resistance theory analysis, the equivalent thermal conductivity of the film was derived. A finite element method (FEM)-based thermal simulation model was developed to systematically study the influence of dust coverage density on the surface temperature of PCBs assembled with various power levels of electronic components. The simulation results were experimentally validated through quartz particle deposition and temperature rise measurements. Experimental results indicate that the surface temperature of the circuit board increases significantly with higher particle coverage density. As the dust coverage density increases from dust-free condition to 1200 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>g/cm², the predicted temperature rise of PCB-mounted chips is an average temperature rise of <inline-formula> <tex-math>$3.6~^{circ }$ </tex-math></inline-formula>C, showing excellent agreement with experimental measurements, with an overall deviation within −3%<inline-formula> <tex-math>$sim!+4$ </tex-math></inline-formula>%. Under the same coverage density, the temperature rise is nearly identical across electronic components with different power ratings. Finally, a theoretical temperature rise model for dust-covered components was established by fitting experimental data. This study demonstrates that modeling deposited particles as a porous medium film provides an efficient and accurate method for predicting the permissible dust coverage threshold of electronic products based on allowable temperature rise limits.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2076-2088"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2026.3728929","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3728929","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"C2-C2"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703949","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2026.3728931","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3728931","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2208-2208"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703882","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of the Interface Reliability of Multilevel Stacked Copper Microvias: Modeling and Simulation","authors":"Syed Mujahid Abbas;Qiang Yu;Michael Pecht","doi":"10.1109/TCPMT.2026.3704315","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3704315","url":null,"abstract":"Microvias serve as electrical interconnections between conducting layers of laminates in high-density interconnect printed circuit boards (PCBs). However, stacked microvias can interfacially separate or crack due to fatigue if not properly designed and manufactured. In this article, seven different types of commercially used microvia configurations, e.g., stacked, staggered, semi-stacked, stacked-on buried via (BV), and stacked offset to BVs, are modeled using finite element analysis to investigate the mechanisms of failure. The simulation results strongly correlate with experimental data, and a novel Coffin–Manson factor was developed to predict the fatigue life of the microvia interface. Insights into the interfacial separation and target pad cracking are then presented.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2054-2067"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact IPD Bandpass Filter With Wide Upper Stopband in GaAs Technology","authors":"Gang Zhang;Yuanming Yan;Yichuan Jiang;Zehua Liu;Na Li;Kam-Weng Tam;Shichang Chen","doi":"10.1109/TCPMT.2026.3716634","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3716634","url":null,"abstract":"A compact bandpass filter (BPF) featuring high selectivity and a wide stopband has been proposed and realized using gallium arsenide (GaAs) integrated passive device (IPD) technology. A developed topology consisting of a T-shape topology and a paralleled capacitor is introduced in this BPF. The T-shape topology can achieve a triple-mode filter response and generate two transmission zeros (TZs) at both sides of the passband, significantly improving the frequency selectivity. This paralleled capacitor can introduce an additional TZ to widen the stopband. For validation, the proposed BPF centered at 3.65 GHz with a 3-dB fractional bandwidth (FBW) of 64% has been fabricated and measured. The measured results show a wide stopband rejection of −20 dB up to 36.7 GHz (about <inline-formula> <tex-math>$10f_{0}$ </tex-math></inline-formula>) and a compact size of <inline-formula> <tex-math>$0.068lambda _{0} times 0.052lambda _{0}$ </tex-math></inline-formula>.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2110-2113"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip-Chip Bonding of 3-D Copper Compressible Microinterconnects for Cryogenic Electronic Packaging","authors":"Euichul Chung;Michael A. Nieves Calderon;Zhonghao Zhang;M. Mert Torunbalci;Martin Damyanov;Georg Aigeldinger;Michael C. Hamilton;Muhannad S. Bakir","doi":"10.1109/TCPMT.2026.3720606","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3720606","url":null,"abstract":"A free-standing copper compressible microinterconnect (CMI) for cryogenic applications was fabricated, flip-chip bonded, and its electrical and mechanical characteristics were analyzed in this letter. To address the increasing demand for reliable off-chip interconnects in cryogenic electronic packaging, we present a pressure-contact-based 3-D copper CMI that exhibits linear elastic behavior, requires a relatively low bonding force, and offers reworkability. Ex-situ resistance measurements at room temperature and in-situ measurements from 300 K down to 14 mK were performed on a flip-chip bonded CMI array, revealing up to a 39.6% reduction in resistance upon cool down. Furthermore, a mechanistic investigation of the flip-chip bonding process was conducted, including force–displacement measurements, along with force–stress analysis using finite element analysis (FEA), to verify robustness.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2204-2207"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-Packaged All-Port CM Reflectionless Balanced Filtering Power Divider Based on SISPSL Structure With Broadband CM Absorption","authors":"Du Chen;Han-Peng Zheng;Xu Jiang;Feng Wei;Hong-Yu Liu","doi":"10.1109/TCPMT.2026.3685442","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3685442","url":null,"abstract":"In this article, a self-packaged all-port common-mode (CM) reflectionless balanced filtering power divider (FPD) with high CM suppression and broadband CM absorption is proposed based on substrate-integrated suspended parallel stripline (SISPSL) for the first time. A ring resonator is utilized to provide differential-mode (DM) filtering and power division response based on the Wilkinson power-divider structure. Two transmission zeros (TZs) are generated by employing a ring resonator, significantly improving DM frequency selectivity. Based on the anti-phase-fed double-sided parallel-stripline (DSPSL) structure, a high CM suppression without affecting the DM performance is achieved in the proposed balanced FPD. Furthermore, the CM energy is absorbed by the resistors loaded between the transmission lines, thereby achieving broadband CM reflectionless characteristics. To validate the design, a prototype of the CM reflectionless balanced FPD was designed and fabricated. The measured results show good consistency with simulated data, confirming the feasibility and effectiveness of the proposed approach.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2127-2134"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on Low-Temperature Thermocompression Bonding of Glass Substrates Assisted by Nano Titanium Passivation Layer","authors":"Zihan Wang;Jihua Zhang;Zhen Fang;Jinxu Liu;Hongwei Chen;Shuqi Li;Borui Li;Wenlei Li;Mingcheng Chen;Wanli Zhang","doi":"10.1109/TCPMT.2026.3724823","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3724823","url":null,"abstract":"Low-temperature Cu–Cu bonding is critical for glass-based 3-D advanced packaging, as conventional high-temperature processes induce severe thermal stress via CTE mismatch. This work investigates Ti-passivation-assisted low-temperature Cu–Cu bonding through molecular dynamics (MDs) simulations and experimental characterization. The results reveal that the Ti layer spontaneously undergoes solid-state amorphization (SSAR) under coupled thermodynamic and kinetic effects: negative Cu–Ti mixing enthalpy drives intermixing, while rapid asymmetric interstitial diffusion of small Cu atoms induces lattice distortion and structural collapse. The resulting amorphous layer acts as an ultrafast diffusion channel with reduced activation energy, enabling dense bonding at <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C with >90% wafer-level effective area and 16 MPa tensile strength. Failure occurs at the glass/Ti film–substrate interface rather than the bonded Cu–Cu interface. These findings provide mechanistic insights and a viable pathway for reliable multilayer glass stacking in high-performance 3-D packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2196-2199"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spatiotemporal Learning in Power Modules: Wavelet-Enhanced Forecasting of Thermomechanical Degradation","authors":"Sanghyeon Chang;Paul Paret;Sreekant Narumanchi;Yoonjin Won","doi":"10.1109/TCPMT.2026.3656473","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3656473","url":null,"abstract":"Detecting internal defects in power electronics packages is critical for their performance and reliability, especially under extreme operating conditions, as these defects can lead to catastrophic failure if not properly addressed. Confocal scanning acoustic microscopy (C-SAM) plays a key role in the nondestructive evaluation of bond layer degradation within a power electronics package by detecting defects such as delamination, voids, and cracks. However, accurately quantifying and predicting these defects from C-SAM images remain significant challenges due to the low noise-to-signal ratio, which typically arises from both the imaging process and the bond patterns themselves. In this article, we explore machine learning strategies for processing C-SAM images and providing predictive models of defect growth. We use C-SAM images of sintered copper and sintered silver samples, which are obtained under accelerated thermal experiments, as the representative dataset for our study. We investigate the effect of Fourier transforms and wavelet transforms on these datasets to remove high-frequency noise and address noise across multiple scales with histogram equalization to enhance the contrast and improve the visibility of defects. As a result, defect boundaries can be clearly distinguished, enabling more accurate tracking of their growth over time. We then employ different time-series forecasting algorithms on the denoised images to formulate an image-based lifetime prediction model. Statistical models and deep learning techniques are trained on images obtained in the early stages of thermal shock, and defect growth in the later stages is predicted. Our work serves as a preliminary attempt to improve the accuracy of lifetime prediction models of power electronics packages, which is critical under extreme operating environments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2025-2035"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Substrate Attachment Voids and Their Impact on VSWR/Insertion Loss Performance for Low-Power Passive Circuits","authors":"Shivendra Tripathi;Anuj Sarode;Satendra Kumar;Deepak Kumar Sharma;Harimohan Singh;Santanu Sinha;Ishwarlal Prajapati","doi":"10.1109/TCPMT.2026.3724946","DOIUrl":"https://doi.org/10.1109/TCPMT.2026.3724946","url":null,"abstract":"Substrate-attachment voids are critical defects in high-reliability RF assemblies, yet their quantitative impact on passive circuit performance is underreported. This study correlates Au₈₀Sn₂₀ solder voiding with the simulated voltage standing wave ratio (VSWR) and measured insertion loss (IL) of miniature hybrid semi-monolithic microstrip lines and bandpass filters (BPF) across C through Ka band. Full-wave 3-D FEM (Ansys HFSS) and MoM planar EM (Keysight ADS Momentum) simulations were validated experimentally on microstrip-line and BPF test vehicles (TVs), respectively. Across void fractions from 4.3% to 44.9%, insertion loss showed no correlation with void content; the largest post-bake deviation observed was –0.33 dB, bounding any void-related effect below that level. A 144-h bake at <inline-formula> <tex-math>$125~^{circ } $ </tex-math></inline-formula>C confirmed electrical stability, with minor fluctuations tied to stress relaxation. The results support distinguishing active-device thermal paths from passive ground paths, avoiding unnecessary rework and reducing manufacturing costs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 9","pages":"2140-2147"},"PeriodicalIF":3.3,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149014403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}