IEEE Transactions on Components, Packaging and Manufacturing Technology最新文献

{"title":"Research on the Key Processes of Large-Area Silver Sintering for SiC Power Modules","authors":"Guiqin Chang;Di An;Erping Deng;Xiang Li;Haihui Luo;Yongzhang Huang","doi":"10.1109/TCPMT.2025.3531127","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3531127","url":null,"abstract":"In this article, an alternative process method was proposed for the large-area silver sintering joint in silicon carbide (SiC) power modules, with integrated drying process. This proposed method significantly simplified the production process of large-area sintering. As a typical application, SiC power modules (1200 V/17 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>, eight chips in parallel) were packaged using the method, achieving a reliable connection between ceramic substrates (<inline-formula> <tex-math>$50times 60$ </tex-math></inline-formula> mm2) and heat sinks. The advantages of the proposed large-area silver sintering have been verified through the assessments of mechanical properties, thermal resistance, and thermal shock reliability. Results indicate that adjusting the silver paste printing thickness can accommodate the warpage of active metal brazing (AMB) substrates. Optimizing the drying temperature and heating rate allows for a structurally uniform and dense large-area sintered silver layer, even with single printing and integrated drying processes. The sintered joint has a porosity of 2%–3%, with no apparent delamination defects. Compared to traditional solder SnSb5, the average shear strength of the silver sintering connection layer has increased by 95%. Under thermal shock conditions (<inline-formula> <tex-math>$- 60~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$+ 150~^{circ }$ </tex-math></inline-formula>C), the silver sintering layer demonstrates excellent reliability, with only a 2% degradation of the connection layer after 1000 cycles. Furthermore, compared to traditional solder (SnSb5), the total thermal resistance of power modules is reduced by 10.3%, effectively enhancing the heat dissipation capacity of the SiC module. In summary, this study identified and resolved key process issues in large-area sintering, providing significant guidance for the packaging of high-power density and high-reliability SiC modules.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"410-420"},"PeriodicalIF":2.3,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ball Grid Array Package Intermittent Partial Connection Defect Analysis in DDR4 Data Channel","authors":"Muhammad Waqar;Young-Bin Chang;Hyeonu Park;Sanghyeon Baeg","doi":"10.1109/TCPMT.2025.3530483","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3530483","url":null,"abstract":"This article analyzes intermittent partial connection defect in double data rate 4 (DDR4) memory data channel. DDR4 ball grid array (BGA) package develops partial connection defect during device operation. The electrical model of defect is presented, and ANSYS software is used to extract resistance, inductance, and capacitance change due to defect radius and defect height variation. ANSYS 3-D electromagnetic field solver simulation is done to extract S-parameters of a pair of solder balls having intermittent partial connection defect. It is shown that there is noticeable signal degradation when defect height is above <inline-formula> <tex-math>$0.1~mu $ </tex-math></inline-formula>m and radius is below 0.1-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m values, and this will result in intermittent errors. AC coupling behavior appears at small defect radius and 3-dB frequency changes with defect height and radius change. DDR4 data channel architecture is examined to show asymmetric behavior for logic “1” and logic “0.” Data channel response is analyzed in the presence of partial connection defect, and data eye channel loss and margin loss are used to characterize signal degradation. The area of partial connection is varied to observe the channel response change. As defect height increases, the radius at which DDR4 data specification violation occurs decreases. Data rate is varied to show channel loss increase for higher data rates. Eye margin is calculated to show decrease in low eye margin with data rate increase. DDR4 data channel asymmetric response causes logic “0” bit error rate to increase, whereas logic “1” bit error rate does not change. This behavior can be used as a diagnostic symptom for intermittent partial connection defect detection.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"367-376"},"PeriodicalIF":2.3,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on Multifault Testing Method for MIV Based on Grid Search and Random Forest","authors":"Yuling Shang;Longlu Geng;Chunquan Li;Zhuofan Song;Jintao Zhang;Junji Li","doi":"10.1109/TCPMT.2025.3530519","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3530519","url":null,"abstract":"With the fast development trend of highly integrated electronic products, as the key technology of 3-D interconnect circuits, the research on monolithic intertier via (MIV) testing technology is particularly critical. Due to the high integration density, the MIV itself is very prone to manufacturing faults, moreover, the uncertainty of fault location, the complexity of fault type, that will have a greater impact on the signal transmission performance of the MIV. Therefore, in order to effectively isolate the faults and reduce the loss of assembly yield, a new nondestructive MIV fault testing method is proposed. The method adopts random forest (RF) classification model optimized based on grid search (GS) optimization algorithm. This test method can effectively solve the problem that traditional MIV test methods are difficult to accurately test for MIV faults. As well as the study of multifault in response to the fact that the existing methods are less studied for the presence of multifault in MIV. The simulation results show that the GS-RF-based MIV fault testing method can avoid damage to the MIV under testing during the MIV fault testing process, and the accuracy of single-fault testing reaches 96.11%, and the accuracy of multifault testing reaches 91.38%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"319-327"},"PeriodicalIF":2.3,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bare-Die Embedding Technique for Highly Integrated Power Electronics for Small Mobility","authors":"Shahid Aziz Khan;Feng Zhou;Mengqi Wang;DucDung Le;Shivam Chaturvedi","doi":"10.1109/TCPMT.2025.3530398","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3530398","url":null,"abstract":"Small mobility vehicles such as electric scooters are becoming an integral part of the transition toward electrified transportation. However, the limited driving range and the lack of onboard charging capability are the major challenges for widespread adaptation, which arises due to the limited space for power electronics units and batteries on the chassis of small mobility vehicles. This research introduces a new bare-die embedding printed circuit board (PCB) packaging technology, ensuring a very compact, high power density, and integrated design for the power electronics unit. The design incorporates the bare die of the switching devices into the PCB layers and uses multilayers for routing and cooling purposes. A silicon (Si) MOSFET bare die is embedded into the FR4 layers using the stomach cell approach, electrically connected, and cooled through laser-drilled micro vias and copper fills. The electrothermal design reduces the parasitic loop inductance by 74%, increases the power density by 113%, and enhances the driving range of the small mobility vehicle by 16.6% compared with the traditional TO-247 packaging approach. Moreover, a new thermal model is also presented and validated for the bare-die embedded board. A high power density power electronics unit integrating the motor drive and the onboard charger was developed using the proposed bare-die embedding technology, and a benchmark comparison was made to evaluate the effectiveness of the proposed bare-die embedding technique.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"613-622"},"PeriodicalIF":2.3,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrothermal Coupling Optimization Method of a 3-D Microsystem Based on the Fast Dual-Cell Method","authors":"Fang-Qian Wang;Xiao-Peng Wu;Guang-Bao Shan;Yin-Tang Yang","doi":"10.1109/TCPMT.2024.3525141","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3525141","url":null,"abstract":"In recent years, due to the increase in power density and thermal accumulation, electrical and thermal reliability have become the main challenges in microsystem design, which requires rapid prediction of the electrical and thermal characteristics of a microsystem. To address these challenges, this study proposes a fast dual-cell method (FDCM) for the electrothermal coupling of 3-D microsystems. By decomposing the constitutive matrix and extracting the temperature variation parameters, the proposed method reduces the number of unknowns of temperature variation iteration, thus ensuring the calculation accuracy while significantly improving the calculation efficiency at a lower memory consumption. Compared with the finite element method (FEM) method, the calculation error of the FDCM is decreased by 1%, the calculation time is reduced by 63.70%, and the calculation memory is only 12.86% of that of the FEM. Finally, this study optimizes the layout of 3-D microsystems using the FDCM, addressing the electrothermal coupling problem.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"263-271"},"PeriodicalIF":2.3,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite-Element Analysis and Multiobjective Optimization of Solder Joint Temperature Difference and Cooling Stress During PCBA Reflow Process","authors":"Jingyi Lan;Chunyue Huang;Ying Liang;Chao Gao;Gui Wang;Zhiqin Cao","doi":"10.1109/TCPMT.2025.3529292","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3529292","url":null,"abstract":"A finite-element analysis model of a printed circuit board assembly (PCBA) was established. The model was subjected to a reflow soldering temperature profile to analyze the temperature distribution at the solder joint solidification moment and the cooling stress distribution at the end of the reflow soldering process. Validation experiments confirmed the accuracy of the simulation results. The response surface methodology (RSM) combined with the NSGA-II algorithm was employed to optimize the reflow soldering process parameters with the dual objectives of minimizing solder joint temperature difference and cooling stress. The results reveal uneven temperature distribution at the solder joint solidification onset and concentrated cooling stress due to the mismatch in thermal expansion coefficients. The optimized reflow soldering process parameters were determined as: soak time of 80 s, reflow time of 35 s, reflow temperature of <inline-formula> <tex-math>$230~^{circ }$ </tex-math></inline-formula>C, and cooling rate of <inline-formula> <tex-math>$2~^{circ }$ </tex-math></inline-formula>C/s. Simulation validation demonstrated that with the optimal reflow soldering process parameters, the solder joint temperature difference and cooling stress were reduced by <inline-formula> <tex-math>$1.058~^{circ }$ </tex-math></inline-formula>C and 1.245 MPa, respectively. The results of this study on the optimization of the reflow soldering process parameters of the PCBA have a certain degree of significance in guiding.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 3","pages":"479-487"},"PeriodicalIF":2.3,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Temperature SLID-TSV Interconnects for 3-D (MEMS) Packaging","authors":"Fahimeh Emadi;Shenyi Liu;Vesa Vuorinen;Mervi Paulasto-Kröckel","doi":"10.1109/TCPMT.2025.3528519","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3528519","url":null,"abstract":"Three-dimensional heterogeneous integration is becoming increasingly important in advanced packaging as device functionalities expand within smaller spaces. Three-dimensional interconnects such as through silicon via (TSV)-solid–liquid interdiffusion (SLID) interconnects offer a promising approach for achieving miniaturization, high integration, and reduced power consumption. However, well-known Cu–Sn SLID-TSVs require high bonding temperatures, leading to residual stress and cracks. This research focuses on developing 3-D interconnects by using Cu–Sn–In/Co SLID-TSVs, which decrease bonding temperatures and reduce these issues. Finite element (FE) simulations qualitatively compared stress states in both SLID-TSV systems, showing lower residual stress in the Cu–Sn–In/Co SLID system than in Cu–Sn SLID. The Cu–Sn–In/Co SLID-TSV underwent microstructural analysis and reliability tests, including high-temperature storage (HTS), thermal shock (TS), and tensile strength testing. Most samples were free of voids and cracks, with a few showing minor defects along the bond line after TS. No cracks were observed inside the Si and TSVs. This indicates that adopting the Cu–Sn–In/Co system and reducing the bonding temperature to 200 °C can effectively prevent crack formations across bond lines, Si, and TSVs. Furthermore, all the samples meet the tensile strength requirements according to MIL-STD-883 method 2027.2, with the highest value observed for HTS-tested samples. Hence, low-temperature 3-D SLID-TSV interconnects were successfully demonstrated, showing strong potential for 3-D MEMS-ICs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"377-386"},"PeriodicalIF":2.3,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839082","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Co-Design and ML-Based Optimization of Through-Via in Silicon and Glass Interposers for Electronic Packaging Applications","authors":"Pouria Zaghari;Sourish S. Sinha;Douglas C. Hopkins;Jong Eun Ryu","doi":"10.1109/TCPMT.2025.3527313","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527313","url":null,"abstract":"Copper-filled via is a critical component of advanced electronic packaging technologies. Embedded in interposer substrate, vias provide enhanced electrical performance in 2.5-D and 3-D electronic packaging by allowing a smaller form factor. In addition to the electrical characteristics of an electronic package, its thermal and mechanical performance also depends on via geometry and the interposer material. This necessitates a co-design approach integrating thermal, mechanical, and electrical considerations. This article focuses on a numerical parametric study and multiobjective machine learning-based optimization of through-silicon via (TSV) and through-glass via (TGV). This study investigates the multidisciplinary effects of aspect ratio (AR) and pitch in the square and hexagonal array vias. Copper protrusion, thermal resistance, and electrical parasitics were used as the optimization performance indicators. An online artificial neural network (ANN) algorithm, as well as the conventional genetic algorithm (GA), was adopted to optimize the through-via designs. The parametric study demonstrated that glass substrates are more effective in reducing copper protrusion and mutual capacitance up to 47.5% and 67.6% compared to silicon. However, TSVs showed superior thermal performance. A higher AR helps minimize the copper protrusion for mechanical performance. Moreover, the thermal performance was enhanced by reducing the pitch and using hexagonal array vias. Regarding electrical performance, a high pitch and low AR are preferable to minimize electrical parasitics. Finally, a 61.3% decrease in the computation time was achieved by using an online ANN-based optimization scheme compared to GA, highlighting its potential in the optimization of high-fidelity complex electronic designs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"295-308"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of S-Parameters for Nonuniform Microstrip Lines With Tabbed Routing Using Analytical-Numerical Method and Machine Learning","authors":"Hanqing Duan;Weijie Dong;Yongping Xie","doi":"10.1109/TCPMT.2025.3527378","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527378","url":null,"abstract":"In this article, a model for characterizing the S-parameters of periodic nonuniform microstrip lines with tabbed routing is proposed, which can calculate the corresponding scattering parameters quickly and accurately from the physical parameters. The model employs an equation-based analytical (EBA) solution, utilizing a piecewise cascade methodology and integrating numerical analysis from the finite difference time domain (FDTD) method within symmetrical repeated regions. This approach mitigates errors resulting from inadequate quasistatic conditions, thereby improving accuracy. Furthermore, the model integrates partial least squares (PLS) machine learning (ML) for correction. It leverages discrepancies between calculated and electromagnetic simulation results as learning inputs to predict model deviations under new structural parameters, thereby enhancing characterization precision. Validation against full-wave simulations confirms the model’s strong alignment and superior accuracy over the EBA solution, without compromising computational efficiency during numerical solution and model training. Moreover, the model’s accuracy is confirmed through comprehensive board fabrication and measurement experiments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"347-355"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tier Transfer of Ultrathin Reconstituted- SiO₂ Chiplet Tiers","authors":"Ashita Victor;Muhannad S. Bakir","doi":"10.1109/TCPMT.2025.3527427","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527427","url":null,"abstract":"Wafer-scale packaging techniques pave the way for achieving high-density integration in advanced chiplet-based architectures. In this letter, a wafer-scale chiplet reconstitution technology is presented, where the key idea is to encapsulate a “sea of chiplets” in low-temperature silicon dioxide (SiO2) to form a reconstituted chiplet tier. For the demonstration of an ultrathin reconstituted-SiO2 chiplet tier, 10–20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick passive chiplets having a chiplet-to-chiplet gap of <inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>m are fabricated. These passive chiplets are then encapsulated in 18–20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick silicon dioxide. However, to enable further postprocessing and fabrication of redistribution layers (RDLs) on the chiplet tiers, temporary bonding and debonding (TBDB) techniques are implemented. This letter explores different tier transfer (TBDB) techniques for the ultrathin SiO2 -chiplet tiers (<40-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick). Two temporary adhesives were evaluated for this purpose: Crystalbond and double-side thermal release tape. The experimental results revealed that the Crystalbond adhesive posed several challenges, while the double-side thermal release tape allowed for a more successful transfer of the ultrathin chiplet tier.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"432-434"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}