Tier Transfer of Ultrathin Reconstituted- SiO₂ Chiplet Tiers

IF 2.3 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-01-08 DOI:10.1109/TCPMT.2025.3527427

Ashita Victor;Muhannad S. Bakir

{"title":"Tier Transfer of Ultrathin Reconstituted- SiO₂ Chiplet Tiers","authors":"Ashita Victor;Muhannad S. Bakir","doi":"10.1109/TCPMT.2025.3527427","DOIUrl":null,"url":null,"abstract":"Wafer-scale packaging techniques pave the way for achieving high-density integration in advanced chiplet-based architectures. In this letter, a wafer-scale chiplet reconstitution technology is presented, where the key idea is to encapsulate a “sea of chiplets” in low-temperature silicon dioxide (SiO2) to form a reconstituted chiplet tier. For the demonstration of an ultrathin reconstituted-SiO2 chiplet tier, 10–20-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m-thick passive chiplets having a chiplet-to-chiplet gap of <inline-formula> <tex-math>$50~\\mu $ </tex-math></inline-formula>m are fabricated. These passive chiplets are then encapsulated in 18–20-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m-thick silicon dioxide. However, to enable further postprocessing and fabrication of redistribution layers (RDLs) on the chiplet tiers, temporary bonding and debonding (TBDB) techniques are implemented. This letter explores different tier transfer (TBDB) techniques for the ultrathin SiO2 -chiplet tiers (<40-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m-thick). Two temporary adhesives were evaluated for this purpose: Crystalbond and double-side thermal release tape. The experimental results revealed that the Crystalbond adhesive posed several challenges, while the double-side thermal release tape allowed for a more successful transfer of the ultrathin chiplet tier.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"432-434"},"PeriodicalIF":2.3000,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10833778/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

Wafer-scale packaging techniques pave the way for achieving high-density integration in advanced chiplet-based architectures. In this letter, a wafer-scale chiplet reconstitution technology is presented, where the key idea is to encapsulate a “sea of chiplets” in low-temperature silicon dioxide (SiO2) to form a reconstituted chiplet tier. For the demonstration of an ultrathin reconstituted-SiO2 chiplet tier, 10–20-

$\mu $

m-thick passive chiplets having a chiplet-to-chiplet gap of

$50~\mu $

m are fabricated. These passive chiplets are then encapsulated in 18–20-

$\mu $

m-thick silicon dioxide. However, to enable further postprocessing and fabrication of redistribution layers (RDLs) on the chiplet tiers, temporary bonding and debonding (TBDB) techniques are implemented. This letter explores different tier transfer (TBDB) techniques for the ultrathin SiO2 -chiplet tiers (<40-

$\mu $

m-thick). Two temporary adhesives were evaluated for this purpose: Crystalbond and double-side thermal release tape. The experimental results revealed that the Crystalbond adhesive posed several challenges, while the double-side thermal release tape allowed for a more successful transfer of the ultrathin chiplet tier.

查看原文本刊更多论文

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

4.70

自引率

13.60%

发文量

203

审稿时长

3 months

期刊介绍： IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.