Ball Grid Array Package Intermittent Partial Connection Defect Analysis in DDR4 Data Channel

Abstract

This article analyzes intermittent partial connection defect in double data rate 4 (DDR4) memory data channel. DDR4 ball grid array (BGA) package develops partial connection defect during device operation. The electrical model of defect is presented, and ANSYS software is used to extract resistance, inductance, and capacitance change due to defect radius and defect height variation. ANSYS 3-D electromagnetic field solver simulation is done to extract S-parameters of a pair of solder balls having intermittent partial connection defect. It is shown that there is noticeable signal degradation when defect height is above $0.1~\mu $ m and radius is below 0.1- $\mu $ m values, and this will result in intermittent errors. AC coupling behavior appears at small defect radius and 3-dB frequency changes with defect height and radius change. DDR4 data channel architecture is examined to show asymmetric behavior for logic “1” and logic “0.” Data channel response is analyzed in the presence of partial connection defect, and data eye channel loss and margin loss are used to characterize signal degradation. The area of partial connection is varied to observe the channel response change. As defect height increases, the radius at which DDR4 data specification violation occurs decreases. Data rate is varied to show channel loss increase for higher data rates. Eye margin is calculated to show decrease in low eye margin with data rate increase. DDR4 data channel asymmetric response causes logic “0” bit error rate to increase, whereas logic “1” bit error rate does not change. This behavior can be used as a diagnostic symptom for intermittent partial connection defect detection.