Co-Design and ML-Based Optimization of Through-Via in Silicon and Glass Interposers for Electronic Packaging Applications

Abstract

Copper-filled via is a critical component of advanced electronic packaging technologies. Embedded in interposer substrate, vias provide enhanced electrical performance in 2.5-D and 3-D electronic packaging by allowing a smaller form factor. In addition to the electrical characteristics of an electronic package, its thermal and mechanical performance also depends on via geometry and the interposer material. This necessitates a co-design approach integrating thermal, mechanical, and electrical considerations. This article focuses on a numerical parametric study and multiobjective machine learning-based optimization of through-silicon via (TSV) and through-glass via (TGV). This study investigates the multidisciplinary effects of aspect ratio (AR) and pitch in the square and hexagonal array vias. Copper protrusion, thermal resistance, and electrical parasitics were used as the optimization performance indicators. An online artificial neural network (ANN) algorithm, as well as the conventional genetic algorithm (GA), was adopted to optimize the through-via designs. The parametric study demonstrated that glass substrates are more effective in reducing copper protrusion and mutual capacitance up to 47.5% and 67.6% compared to silicon. However, TSVs showed superior thermal performance. A higher AR helps minimize the copper protrusion for mechanical performance. Moreover, the thermal performance was enhanced by reducing the pitch and using hexagonal array vias. Regarding electrical performance, a high pitch and low AR are preferable to minimize electrical parasitics. Finally, a 61.3% decrease in the computation time was achieved by using an online ANN-based optimization scheme compared to GA, highlighting its potential in the optimization of high-fidelity complex electronic designs.