IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme","authors":"Yishuo Meng;Jianfei Wang;Siwei Xiang;Jia Hou;Zhijie Lin;Kuizhi Mei;Chen Yang","doi":"10.1109/TCSI.2025.3554332","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554332","url":null,"abstract":"Convolutional neural networks (CNNs) are evolving as they are applied to more diverse environments and more difficult challenges. The evolving induces various convolution modes (e.g., <inline-formula> <tex-math>$1times 1$ </tex-math></inline-formula> convolution, 2-stride convolution and rectangle convolution) in current CNNs and makes it difficult for the hardware accelerators to efficiently support such various convolution modes. In this paper, it is found that an important difference of these convolution modes is the computation density. Therefore, the above convolution modes are regarded as structured sparse and claims that sparse-based design methodology can be applied for the implementation of the reconfigurable CNN accelerator. Subsequently, two critical architectural parameters, including input tile size and convolution engine (CE) scale, are evaluated based on Standard deviation of calculations (SDC), unsupported convolution mode (UCM) and unsuitable I FM size (UIS), DSP utilization ratio (DUR) as well as hardware resource overhead (HRO), respectively. With the aid of the optimal parameters, a high-parallelism and flexible CE array and a high-performance and reconfigurable CNN architecture are designed. The accelerator was implemented on a Xilinx VC709 FPGA and ran at a clock frequency of 300 MHz, achieving 921.60 to 1382.40 GOPS while supporting various convolution modes. Compared with previous dense-/sparse-based works, the proposed accelerator can realize <inline-formula> <tex-math>$1.35times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$10.77times $ </tex-math></inline-formula> improvements on performance and <inline-formula> <tex-math>$1.22times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$2.84times $ </tex-math></inline-formula> improvements on DSP efficiency while deploying VGG16.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3983-3996"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rational-Exponent Filters with Applications to Generalized Exponent Filters","authors":"Samiya A. Alkhairy","doi":"10.1109/TCSI.2025.3545459","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3545459","url":null,"abstract":"We present filters with rational exponents in order to provide a continuum of filter behavior not classically achievable. We discuss their stability, the flexibility they afford, and various representations useful for analysis, design and implementations. We do this for a generalization of second-order filters which we refer to as rational-exponent Generalized Exponent Filters (GEFs) that are useful for a diverse array of applications. We present equivalent representations for rational-exponent GEFs in the time and frequency domains: transfer functions, impulse responses, and integral expressions - the last of which allows for efficient real-time processing without preprocessing requirements. Rational-exponent filters enable filter characteristics to be on a continuum rather than limiting them to discrete values thereby resulting in greater flexibility in the behavior of these filters without additional complexity in causality and stability analyses compared with classical filters. In the case of GEFs, this allows for having arbitrary continuous rather than discrete values for filter characteristics such as 1) the ratio of 3dB quality factor to maximum group delay - particularly important for filterbanks which have simultaneous requirements on frequency selectivity and synchronization; and 2) the ratio of 3dB to 15dB quality factors that dictates the shape of the frequency response magnitude.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2139-2152"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Observability Verification System Analysis for Observability and Reconstructibility of Probabilistic Logical Control Networks","authors":"Yalu Li;Haitao Li;Gaoxi Xiao","doi":"10.1109/TCSI.2025.3553463","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553463","url":null,"abstract":"Observability and reconstructibility are two fundamental issues in modern control theory, which are important in both state estimation and observer design. The existing results for verifying the observability and reconstructibility of probabilistic logical control networks (PLCNs) have exponential complexities. This article presents a new approach to verify the observability and reconstructibility of PLCNs, which can greatly reduce the computational complexity. Specifically, the problem is tackled in three different steps. Firstly, based on the division of the state pair space, an observability verification system is established. Secondly, the equivalence between the stabilization of the proposed observability verification system and the observability of PLCNs is revealed, and a new criterion is established to solve the observability of PLCNs. Under the framework, the computational complexity is discussed. Thirdly, the relationship between observability and reconstructibility of PLCNs is unveiled, and some new criteria are established to solve two kinds of reconstructibility problems for PLCNs. Finally, an example of a biological network, apoptosis network, is presented to demonstrate the feasibility of the methods proposed in this article.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4273-4283"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Generalized Discrete-Time Variable Gain ADRC for Nonlinear Systems and Its Application to Parallel Teleoperated Manipulators","authors":"Shaomeng Gu;Jinhui Zhang;Long Cheng;Yuanqing Wu","doi":"10.1109/TCSI.2025.3555204","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555204","url":null,"abstract":"In this paper, we propose a novel generalized discrete-time variable gain active disturbance rejection control (DTVGADRC) method for the <italic>n</i>-th order discrete-time nonlinear systems. The error-driven generalized DTVGADRC can dynamically improve the control performances, including generalized discrete-time variable gain tracking differentiator (DTVGTD), generalized discrete-time variable gain extended state observer (DTVGESO), and generalized discrete-time variable gain controller (DTVGC). Furthermore, the stability analysis of generalized DTVGADRC is performed, and the parameters in the variable gain functions are determined by the theoretical analysis. Finally, the generalized DTVGADRC method is applied to parallel teleoperated manipulators, and the experiment results are presented to illustrate effectiveness of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2868-2877"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Multi-View Cross-Attention Accelerator for Vision-Centric 3D Perception in Autonomous Driving","authors":"Dongxu Lyu;Zhenyu Li;Yansong Xu;Gang Wang;Wenjie Li;Yuzhou Chen;Liyan Chen;Weifeng He;Guanghui He","doi":"10.1109/TCSI.2025.3555837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555837","url":null,"abstract":"Vision-centric 3D perception has become a key mechanism in autonomous driving. It achieves exceptional perceptual performance mainly by introducing a novel attention, multi-view cross-attention (MVCA), for learnable feature extraction and fusion from surround-view cameras. Despite its superiority, MVCA encounters severe inefficiencies in sample, processing elements (PE), and pipelined processing, owing to the redundant and non-uniform sampling-aggregation and rigorous inter-operator dependencies. To address these issues, this article proposes a dedicated MVCA accelerator, MVAtor, with algorithm-architecture co-optimization for vision-centric 3D perception based on multi-view inputs flexibly. For sample inefficiency, a 3-tier hybrid static-dynamic sample and a sensitivity-aware feature pruning approach are proposed to eliminate the 86.03% sample overhead and 24.48% memory requirement, only incuring <1%> <tex-math>$53.7sim 96.1$ </tex-math></inline-formula>% energy-delay product reduction. For pipeline inefficiency, a fine-grained-tiling assisted highly-pipelined architecture is constructed in MVAtor by exploiting the decoupling opportunities on inter-view sparsity, thereby saving 61.03% external memory access while boosting the overall throughputs by <inline-formula> <tex-math>$1.83times $ </tex-math></inline-formula>. Extensively evaluated on representative benchmarks, MVAtor attains <inline-formula> <tex-math>$1.38sim 7.67times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.67sim 11.15times $ </tex-math></inline-formula> improvement on energy and area efficiency respectively, compared to the state-of-the-art related accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3272-3285"},"PeriodicalIF":5.2,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Beam-Steering dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128 × 80 SPAD Sensor, and ML-Based Edge-Computing Object Detection","authors":"Yifan Wu;Miao Sun;Sifan Zhou;Tao Xia;Lei Wang;Jier Wang;Yuan Li;Ming Zhong;Rui Bai;Xuefeng Chen;Yuanjin Zheng;Patrick Yin Chiang;Shenglong Zhuo;Lei Qiu","doi":"10.1109/TCSI.2025.3550450","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550450","url":null,"abstract":"In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a <inline-formula> <tex-math>$128times 80$ </tex-math></inline-formula> resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a <inline-formula> <tex-math>$128times 80$ </tex-math></inline-formula> SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2089-2102"},"PeriodicalIF":5.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices","authors":"Hoai Luan Pham;Thi Diem Tran;Vu Trung Duong Le;Yasuhiko Nakashima","doi":"10.1109/TCSI.2025.3553837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553837","url":null,"abstract":"Classification is a crucial aspect of cardiovascular-related challenges, requiring thorough research and optimization to develop effective solutions for both patients and doctors. Recently, rapid advancements in artificial intelligence, particularly Convolutional Neural Networks (CNNs), have introduced numerous effective methods, significantly improving disease classification in Electrocardiogram (ECG) analysis. However, existing CNN-based accelerators often encounter challenges such as high parameter counts, limited flexibility in handling diverse CNN configurations, and inefficient hardware utilization. To address these issues, this paper proposes the Mini InceptionNet Accelerator (MINA), a hardware-efficient and flexible accelerator designed specifically for one-dimensional (1-D) CNN-based ECG classification. First, a novel 1-D CNN model, Mini InceptionNet, reduces the parameter count by 41.6% compared to the smallest existing 1-D CNN, minimizing memory requirements while maintaining high classification accuracy. Second, a flexible Processing Element Array (PEA) is designed with a Sharing Buffer Allocator (SBA) to support dynamic data coordination across various network topology parameters. Third, each Processing Element (PE) is equipped with four Local Data Memories (LDMs) and an ALU, enabling efficient intermediate data storage and versatile operations for modern CNN models. To demonstrate its effectiveness, MINA has been successfully implemented and verified on the ZCU102 FPGA at the system-on-chip level. FPGA evaluations show that MINA achieves <inline-formula> <tex-math>$1.3times - 2.9times $ </tex-math></inline-formula> higher energy efficiency (<italic>GOP/s/MeLUT</i>) than state-of-the-art 2-D CNN accelerators. Compared to existing 1-D CNN accelerators, MINA achieves at least <inline-formula> <tex-math>$1.53times $ </tex-math></inline-formula> improvement in the area-delay product (ADP). Additionally, weight pruning is discussed as a supporting strategy, achieving up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> faster inference time and a <inline-formula> <tex-math>$2.13times $ </tex-math></inline-formula> improvement in ADP at 70% sparsity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2740-2753"},"PeriodicalIF":5.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memristor-Emulator-Based Crossbar Array for Object Detection and Recognition","authors":"Jagveer Singh Verma;Prashant Kumar;Basit Shafat Makhdoomi;Rajeev Kumar Ranjan;Sung-Mo Kang","doi":"10.1109/TCSI.2025.3553058","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553058","url":null,"abstract":"Object detection and recognition are crucial for autonomous vehicles, surveillance systems, and human-computer interaction. We present a new fully complementary metal-oxide semiconductor (CMOS) circuit-based system for object detection and recognition using a Spiking Neural Network (SNN). Our holistic CMOS circuit integrates neuromorphic elements, including a leaky integrate-and-fire (LIF) neuron model, spike time-dependent plasticity (STDP) memristor synapse, and basic analog and digital building blocks. The learning mechanism is manifested by a completely different approach based on an array of XOR gates to recognize six different objects with <inline-formula> <tex-math>$256 times 6$ </tex-math></inline-formula> size crossbar arrays. This is the first-ever recognition mechanism of its kind. We also perform handwritten digit recognition using a <inline-formula> <tex-math>$64 times 4$ </tex-math></inline-formula> size array using grayscale conversion. The proposed system’s robustness is validated through process corner simulations, noise analysis, and temperature analysis. We also show the accuracy of our design for the digit recognition task using a confusion matrix plot, and the accuracy turns out to be 82.5 %. Our pioneering approach using a CMOS memristor-emulator STDP crosspoint array-based architecture achieves minimal energy consumption per neuron block, which amounts to <inline-formula> <tex-math>$approx ~2.59$ </tex-math></inline-formula> pJ per neuron block and an overall energy budget of 663.66 pJ for the entire system considering the object recognition task.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4115-4126"},"PeriodicalIF":5.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Application of Brain-Inspired Circuit With Context-Dependent and State-Dependent Memory","authors":"Gang Dou;Daoguo Li;Mei Guo;Herbert Ho-Ching Iu","doi":"10.1109/TCSI.2025.3554171","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554171","url":null,"abstract":"The context and the state of mind are important retrieval cues for long-term memory, which helps information to be retrieved quickly. However, most memristive circuits focus on the process of information memory, few studies consider the process of information retrieval. In this work, a brain-inspired circuit with context-dependent and state-dependent memory is proposed based on the three-level processing model of memory information, which integrates the processes of information memory and information retrieval. The circuit includes sensory memory module, short-term memory module, long-term memory module, information retrieval module, status module, and context module. In the circuit, information, contexts, and states are eventually transferred to long-term memory module for storage and retrieval. Meanwhile, the factors influencing information retrieval are considered, such as the degree of information memory, the time interval between information memory and retrieval, the context, and the state. And the proposed circuit has scalability, which realizes the memory of information in multiple contexts. Finally, based on the characteristics of memristors, the proposed circuit is extended for detecting damage to the machining accuracy of the mobile CNC lathe. Combining brain-inspired circuits with human memory mechanism, this work provides further reference for the research of brain-like intelligence.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2566-2577"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System","authors":"Sayan Sarkar;Yuan Yao;Wing-Hung Ki;Chi-Ying Tsui","doi":"10.1109/TCSI.2025.3550479","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550479","url":null,"abstract":"A 13.56-MHz wireless power transfer (WPT) system with fully integrated transmitter (<inline-formula> <tex-math>${mathrm {T}}_{mathrm {X}}$ </tex-math></inline-formula>) and receiver (<inline-formula> <tex-math>${mathrm {R}}_{mathrm {X}}$ </tex-math></inline-formula>) chips is presented. The receiver’s output voltage is locally regulated using a linear current-sink-based regulator, while global power regulation is achieved at the transmitter through a hybrid control strategy that combines constant off-time and hysteretic control for a reconfigurable power amplifier. Synchronized load-shift keying at the receiver improves the relative change in the primary current of the transmitter by >15%. The adaptive digitally controlled active rectifier achieves a voltage conversion ratio (VCR) and power conversion efficiency (PCE) of 0.92 and 92.4%, respectively, for a <inline-formula> <tex-math>$200~Omega $ </tex-math></inline-formula> load resistance. The end-to-end efficiency is improved by 25% at heavy load and 14% at light load by enabling TX global power regulation. Both TX and RX chips were fabricated in the BCDlite 180 nm process with 1.8 V/5 V devices. This system achieves a greater operating distance, higher output power, and faster load-transient response while significantly reducing circuit and system design complexity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2061-2074"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}