IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Instruction-Based High-Performance Hardware Controller of CRYSTALS-Kyber With Balanced Resource Utilization","authors":"Yijun Cui;Jiansheng Chen;Ziying Ni;Zhuoyao Zhang;Chenghua Wang;Weiqiang Liu","doi":"10.1109/TCSI.2025.3547799","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547799","url":null,"abstract":"Post-quantum cryptography (PQC) aims to ensure information security in the era following the emergence of quantum computers. Lattice-based cryptography (LBC) algorithms have shown significant promise in the standardization process of post-quantum cryptography. This paper proposes an instruction-based high-performance hardware controller of CRYSTALS-Kyber. By designing a highly flexible instruction-based architecture, the control unit evenly distributes instructions and enables independent control of internal modules, significantly enhancing the scalability and adaptability of the hardware. Additionally, the integration of a reconfigurable polynomial operation array (RPOA) unit and optimization of data storage formats further improve computational efficiency and resource utilization. Implementation results on Artix-7 FPGA show that the architecture operates at a frequency exceeding 300 MHz, achieving a performance improvement of 41.3% to 170% compared to the latest designs, while significantly reducing resource overhead. The resource costs for the three security levels are 8112 LUTs, 6077 FFs, and 2523 SLICEs, respectively, with overall computation times of <inline-formula> <tex-math>$34.7~mu s$ </tex-math></inline-formula>, <inline-formula> <tex-math>$53.4~mu s$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$78.5~mu s$ </tex-math></inline-formula>. The proposed design demonstrates outstanding performance, resource efficiency, and energy consumption, providing an efficient and cost-effective hardware solution for the practical deployment of post-quantum cryptography.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2394-2407"},"PeriodicalIF":5.2,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Analysis of Passive-Integrated Absorptive Flat-Group-Delay RF Bandpass Filters in GaAs Technology for Digital Communications","authors":"Nasrin Iranpour;Li Yang;Roberto Gómez-García;Xi Zhu","doi":"10.1109/TCSI.2025.3546509","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3546509","url":null,"abstract":"A family of on-chip passive-integrated absorptive flat-group-delay RF bandpass filters (BPFs) in gallium arsenide (GaAs) technology is presented. These wideband BPFs feature broadband quasi-reflectionless behavior along with quasi-constant group-delay responses beyond their associated 3-dB-bandwidth (BW) ranges. Firstly. by means of a <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-shape network composed of a reflective first-order BPF and two shunt identical lossy bandstop filters (BSFs), a two-port-absorptive RF BPF is engineered. To further increase the stopband attenuation levels, the extension of this filter concept to higher-rejection BPFs using <italic>n</i> cascaded reflective single-pole BPF units and (<inline-formula> <tex-math>${n} +1$ </tex-math></inline-formula>) replicas of a shunt lossy BSF is then approached. Subsequently, in order to equip such BPFs with higher-selectivity filtering responses, the development of input- and two-port-reflectionless BPFs with multiple transmission zeros (TZs) is addressed. Moreover, a multi-TZ flat-group-delay BPF with input-absorptive behavior is devised. It exploits a reflective BPF channel, which is shaped by a high-selectivity BPF unit with two close-to-passband TZs and a shunt series-<italic>LC</i> resonator that produces an additional TZ, along with a shunt absorptive BSF in a complementary-diplexer-based topology. Finally, by cascading two duplicated high-selectivity BPFs and the associated absorptive BSFs with a modified shunt series-<italic>LC</i> resonator in a back-to-back connection, a type of two-port-reflectionless BPF with multiple TZs is further engineered. Following this approach, a modified shunt lossy BSF instead of the previous shunt series-<italic>LC</i> resonator is employed in the overall reflectionless BPF to obtain a sharper-rejection passband and flatter group delay versus the corresponding beyond-3-dB BW. The RF operational foundations of these absorptive BPFs are detailed with analyses of their relevant lumped-element-based equivalent circuits. Furthermore, proof-of-concept prototypes for the five suggested RF BPFs are simulated, built, and measured to experimentally validate their design concepts for application in power-efficient high-data-rate digital-communication systems.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2639-2652"},"PeriodicalIF":5.2,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic Nonlinear Resistance Model for a Power MOSFET in an Oscillatory RLC Circuit","authors":"Soniya Raju;D. Alistair Steyn-Ross;Marcus Wilson;Nihal Kularatna","doi":"10.1109/TCSI.2025.3542754","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3542754","url":null,"abstract":"This paper presents the development of a new M<sc>atlab mosfet</small> model specifically designed for RLC circuits. The key contribution is the formulation of a novel equation that accurately captures the device behavior across subthreshold, above-threshold regions and at threshold point, addressing limitations in existing models. The developed model treats the <sc>mosfet</small> as a variable resistance element, with the resistance changing dynamically at each instant, enabling the solution of differential equations governing the RLC circuit. Curve fitting and refinement were conducted based on experimental results, leading to a close match between the simulations and experimental data. The model was tested with triangle, sinusoidal and quadrilateral gate voltages, and the simulation results show good match with the experimental data, demonstrating the model’s accuracy. It provides a straightforward way to predict performance, making it easier to refine and optimize the design gate voltage before physical implementation. This work provides a solid foundation for <sc>mosfet</small> modeling in oscillatory RLC circuits, which can be applied to a wide range of power electronics applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2792-2803"},"PeriodicalIF":5.2,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An On-Board Satellite Multispectral and Hyperspectral Compressor (MHyC): An Efficient Architecture of a Simple Lossless Algorithm","authors":"Vijay Joshi;J. Sheeba Rani","doi":"10.1109/TCSI.2025.3545127","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3545127","url":null,"abstract":"On-board satellite remote sensing necessitates the data processing blocks to comprise high throughput with low computational complexity to match the high-speed data acquisition with the constraints of resource, power, timing, and downlink bandwidth. This paper presents a high-performance architecture of a simple lossless algorithm (SLA) for on-board satellite multispectral and hyperspectral data compression, which can be configured to all the directional modes of SLA in the band-sequential (BSQ) sampling order. The architecture supports a 16-bit input dynamic range and includes a mode synchronized data handling block along with pipelined implementations of the pre-processing and entropy encoding blocks. A novel adaptation is proposed in the entropy encoder block, which uses a correlation-based adaptation (CBA) in Golomb-Rice (GR) encoding to improve the compression performance of SLA while maintaining the low computational complexity. Kintex KCU-105 evaluation board is used for implementation of the architecture for testing with standard test datasets from the Consultative Committee for Space Data System (CCSDS) corpus of data for multispectral and hyperspectral imagery. The proposed architecture shows comparable compression performance to the low complexity mode of the CCSDS 123.0-B-1 standard and is within <inline-formula> <tex-math>$approx 1$ </tex-math></inline-formula> bits per sample (bps) range in comparison to the default mode of the standard. A throughput of <inline-formula> <tex-math>$approx 4$ </tex-math></inline-formula> Gbps is achieved at a clock frequency of 250 MHz with lesser resource utilization and power consumption compared to the CCSDS 123.0-B-1 standard implementations.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2167-2177"},"PeriodicalIF":5.2,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2025.3541500","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3541500","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10905061","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2025.3541498","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3541498","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1495-1495"},"PeriodicalIF":5.2,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10905059","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2025.3541496","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3541496","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10905062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Consistency Enhancement Technique for MIMO Power Amplifier Modules","authors":"Zhenyu Li;Zhijiang Dai;Zhiqing Liu;Weimin Shi;Jingzhou Pang;Shengdong Hu;Mingyu Li","doi":"10.1109/TCSI.2025.3543689","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3543689","url":null,"abstract":"Hybrid beamforming reduces the hardware complexity of massive multiple-input multiple-output (MIMO) systems. In this architecture, one digital chain must drive all the power amplifiers (PAs) in the subarray. However, differences in PAs lead to poor linearization of shared digital pre-distortion (DPD). Based on circuit mechanisms and model simulations of PAs, this article identifies one reason for differences in PAs. Fluctuations in the manufacturing process lead to changes in the matching network of PAs, and the transmission characteristics of the matching network affect the nonlinear behavior of PAs. In order to reduce the network differences of PAs at the circuit level and improve the consistency of nonlinear behavior, this article proposes a consistency improvement scheme for MIMO power amplifier (PA) modules. The scheme uses the tuned network to correct the differences in the matching network. To validate the scheme, seven PAs from the same batch are corrected by the tuned network. Before and after the correction, the other PAs are linearized by the DPD signal of one PA. The measured bandwidths include 10 MHz and 40 MHz, and the measured power ranges from saturated average power to back-off of 9 dB. The results show that the PAs corrected by the tuned network have a better consistency. The linearization ability of the shared DPD one-drive-multiple is improved. The adjacent channel power ratio (ACPR) improvement reaches 14 dB.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2928-2941"},"PeriodicalIF":5.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Theory and Design of Pseudo-Doherty Load-Modulated Double Balanced Amplifier With Intrinsic Insensitivity to Antenna VSWR","authors":"Jiachen Guo;Pingzhu Gong;Kenle Chen","doi":"10.1109/TCSI.2025.3543818","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3543818","url":null,"abstract":"This paper presents a novel Double-Balanced power amplifier (PA) architecture with an intrinsic load isolation. Derived from the generic load modulated balanced amplifier (LMBA), by designing the single-ended control amplifier (CA) as another balanced PA, the Pseudo-Doherty load-modulated double-balanced amplifier (PD-LMDBA) can inherit the intrinsic load-mismatch tolerance of balanced amplifier without any reconfiguration and load-impedance sensing. Theoretical analysis reveals that both the control amplifier (CA, as carrier) and primary balanced amplifier (BA, as peaking) exhibit complementary load modulation trajectories for their sub-amplifiers (CA1 and CA2, BA1 and BA2) under mismatch. This allows the PA to inherit the intrinsic load insensitivity from the generic quadrature-balanced amplifier and sustain nearly constant performance against arbitrary load variations. A prototype is implemented at 2.1 GHz, achieving 76.2% efficiency at peak power and 69.5% at 10-dB OBO with matched load. Under a <inline-formula> <tex-math>$2:1$ </tex-math></inline-formula> voltage standing wave ratio (VSWR) of load mismatch, an efficiency up to 72.5% at peak power and 64.1% at 10-dB OBO are measured. In modulated evaluation with a 20-MHz OFDM signal, the PA maintains linearity against <inline-formula> <tex-math>$2:1$ </tex-math></inline-formula> VSWR, with 2.1% of error vector magnitude (EVM) and down to -39.5 dB adjacent channel power ratio (ACPR), closely approximating the matched condition.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2048-2060"},"PeriodicalIF":5.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Transform Accelerator With Fast Kernel Selection and Efficient Transform Circuit","authors":"Zhijian Hao;Chenlong He;Jiaming Liu;Qi Zheng;Jinchang Xu;Peijun Ma;Xiaohua Ma;Yue Hao","doi":"10.1109/TCSI.2025.3543575","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3543575","url":null,"abstract":"The introduction of multiple transform types into the Versatile Video Coding (VVC) standard has yielded notable encoding gains but also resulted in substantial computational burdens, posing two critical challenges for hardware implementation: fast kernel selection and efficient transform computation design. Existing studies typically address these challenges in isolation, lacking a holistic solution for VVC transform coding. In this paper, we presents a groundbreaking transform accelerator that unifies transform kernel selection and multiple transform circuit within a single framework. In terms of algorithms, driven by mechanistic analysis, we propose a decision tree-based kernel selection algorithm that ensures both high decision accuracy and computational efficiency. Additionally, we design a transfer matrix-based approximation algorithm for Discrete Sine Transform Type-7 and a matrix decomposition-based improved computation for Discrete Cosine Transform Type-2, significantly reducing the computational complexity. On the hardware front, we implement a high-precision and area-efficient transform accelerator, which integrates highly pipelined kernel selection and transform computation architectures. With multiple reuse and parallelism strategies, the accelerator demonstrates substantial resource efficiency advantages. Experimental results reveal that the proposed accelerator achieves a circuit resource reduction of over 44% with a slight performance degradation, while maintaining processing capabilities up to 8K@57 fps. To the best of our knowledge, this is the first comprehensive hardware solution for VVC transform coding that jointly addresses the challenges of kernel selection and transform circuit design.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2726-2739"},"PeriodicalIF":5.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}