IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"MBM PUF: A Multi-Bit Memory-Based Physical Unclonable Function","authors":"Peyman Dehghanzadeh;Soumyajit Mandal;Swarup Bhunia","doi":"10.1109/TCSI.2025.3526884","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526884","url":null,"abstract":"This paper introduces multi-bit memory-based PUF (MBM PUF), a new PUF architecture designed to enhance the resilience of SRAM PUFs in ASIC applications. The MBM PUF utilizes an SRAM cell as its main component, capitalizing on its simplicity while mitigating weaknesses such as susceptibility to environmental noise and various attacks. As an example, a MBM PUF was implemented within an edge-triggered D flip-flop, a key component in the scan chain used by digital and mixed-signal designs, to achieve enhanced security with minimal area overhead. The concept can also be integrated into other circuits with built-in positive feedback loops, effectively leveraging their resources while minimizing die area. Simulation results in 45 nm CMOS technology show that the proposed security solution can readily fulfill the required performance criteria for a PUF.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2114-2127"},"PeriodicalIF":5.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editorial A New Exciting Year Ahead for TCAS-I","authors":"José M. De La Rosa","doi":"10.1109/TCSI.2024.3507472","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3507472","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"1-1"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10835846","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3513753","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513753","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10835845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3513755","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513755","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"481-481"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10835840","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3513757","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513757","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10836124","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault Tolerant Observer Design for a Class of Re-Entrant Manufacturing Systems","authors":"Hao Sun;Qing Gao;Jianbin Qiu;Steven X. Ding;Jinhu Lü","doi":"10.1109/TCSI.2024.3514674","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3514674","url":null,"abstract":"This paper investigates the fault-tolerant observer design problem for a class of re-entrant manufacturing systems (RMSs) in the presence of workstation faults during the production process. A hyperbolic hybrid partial differential equation (HHPDE) continuum model is constructed to describe the dynamics of RMSs suffering from unexpected workstation faults, by considering that machinery failures of workstations lead to discarding of defective products. In the case that the faults are known, a fault-tolerant impulsive observer is designed for state estimation of the RMSs. In the case that the fault information is uncertain, a diagnostic observer based residual evaluation logic is developed for fault detection first. Upon detecting the faults, an adaptive impulsive observer is then proposed to simultaneously estimate both the system states and the faults. In addition, by using a piecewise Lyapunov function candidate, sufficient stability conditions that guarantee the exponential input-to-state stability (EISS) of the estimation error are formulated in terms of linear matrix inequalities (LMIs). Finally, the feasibility and effectiveness of the proposed strategy are validated through numerical simulations.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1773-1786"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accurate Hardware Predictor for Epileptic Seizure","authors":"Kasem Khalil;Ashok Kumar;Magdy Bayoumi","doi":"10.1109/TCSI.2024.3524513","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3524513","url":null,"abstract":"Epilepsy triggers seizures, which develop before clinical onset in patients, and a timely and accurate prediction can save lives. A research challenge is to design accurate, fast, and energy-efficient hardware predictors. This work advances hardware-based seizure prediction research by proposing a new machine-learning-based predictor. It proposes a novel reconfigurable electroencephalogram (EEG) signal segmentation for increased learning. The proposed reconfigurable segmentation adaptively adjusts the overlap extent between consecutive segments and prepares new segments. Such prepared segments are fed into a Convolutional Auto-Encoder (CAE) using a proposed convolution module. The proposed convolution module uses optimized hyperparameters, including the number of layers, filters, filter size, pooling method, stride value, and padding for high learning and feature extraction. The learned CAE feeds into an Economic Long Short-Term Memory (ELSTM) to attain the final prediction result. The proposed predictor achieves high accuracy by exploiting the temporal dynamics of epileptic activity. It predicts seizures with an accuracy of 99.32%, a sensitivity of 99.29%, and a false alarm rate of 0.003 per hour, yielding high performance across classification thresholds, incurring low costs, and outperforming related hardware solutions. It is implemented in stand-alone VHDL, Altera Arria 10 GX FPGA, and synthesized into 45-nm technology.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2153-2166"},"PeriodicalIF":5.2,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 36.8-μW 66 nV/√Hz 85.7 dB-System-SNDR Reconfigurable Single-Channel ExG Acquisition System for Bio-Sensor Modules","authors":"Yuke Shen;Jiacheng Liu;Kui Wen;Yanbo Zhang;Yi Shen;Shubin Liu;Zhangming Zhu","doi":"10.1109/TCSI.2024.3523502","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3523502","url":null,"abstract":"This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula><inline-formula> <tex-math>$Sigma $ </tex-math></inline-formula>) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC) <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula><inline-formula> <tex-math>$Sigma $ </tex-math></inline-formula> modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula><inline-formula> <tex-math>$text {V}_{text {rms}}$ </tex-math></inline-formula> (0.5-100 Hz) and 1.93 to 3.51 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula><inline-formula> <tex-math>$text {V}_{text {rms}}$ </tex-math></inline-formula> (0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-<inline-formula> <tex-math>$text {V}_{text {pp}}$ </tex-math></inline-formula> differential input and can support 16<inline-formula> <tex-math>$times $ </tex-math></inline-formula> power/BW reconfigurability with ENOB>15 bit. The complete system occupies an active area of 0.56 mm2 and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1068-1080"},"PeriodicalIF":5.2,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation","authors":"Cristian Sestito;Shady Agwa;Themis Prodromakis","doi":"10.1109/TCSI.2024.3522351","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3522351","url":null,"abstract":"Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost between the computing cores and the memory is a way to mitigate the energy consumption. Systolic arrays are suitable architectures to achieve this objective: they use multiple processing elements that communicate each other to maximize data utilization, based on proper dataflows like the weight stationary and row stationary. Motivated by this, we have proposed TrIM, an innovative dataflow based on a triangular movement of inputs, and capable to reduce the number of memory accesses by one order of magnitude when compared to state-of-the-art systolic arrays. In this paper, we present a TrIM-based hardware architecture for CNNs. As a showcase, the accelerator is implemented onto a Field Programmable Gate Array (FPGA) to execute the VGG-16 and AlexNet CNNs. The architecture achieves a peak throughput of 453.6 Giga Operations per Second, outperforming a state-of-the-art row stationary systolic array up to <inline-formula> <tex-math>$sim 3 times $ </tex-math></inline-formula> in terms of memory accesses, and being up to <inline-formula> <tex-math>$ sim 11.9 times $ </tex-math></inline-formula> more energy-efficient than other FPGA accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2263-2273"},"PeriodicalIF":5.2,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Unified Accelerator for All-in-One Image Restoration Based on Prompt Degradation Learning","authors":"Siyu Zhang;Qiwei Dong;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TCSI.2024.3519532","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519532","url":null,"abstract":"All-in-one image restoration (IR) recovers images from various unknown distortions by a single model, such as rain, haze, and blur. Transformer-based IR methods have significantly improved the visual effects of the restored images. However, deploying complex IR models on edge devices is challenging due to massive parameters and intensive computations. Moreover, existing accelerators are typically customized for a single task, resulting in severe resource underutilization when executing multiple tasks. Therefore, this paper develops an algorithm-hardware co-design framework to accelerate a novel CNN-Transformer cooperative model for multiple IR tasks. Firstly, on the algorithm level, an Efficient Restoration Foundational Model (ERFM) is proposed to recover corrupted images from various degradations with low model complexity. Secondly, to guide adaptive corruption removal, a novel prompt learning scheme is introduced to fuse context-related degradation cues and boost high-quality reconstruction. Thirdly, on the hardware level, an integer approximation method is proposed to avoid expensive hardware overhead caused by complex nonlinear operations, such as layer normalization and softmax while maintaining comparable IR quality. Moreover, a head stationary dataflow and softmax fusion mechanism are designed to reduce data movement and enhance on-chip resource utilization. Finally, an overall hardware architecture is developed and implemented in TSMC 28 nm CMOS technology. Experimental results show that our ERFM achieves better visual perception than other baselines on seven challenging IR tasks without task-specific fine-tuning. Moreover, compared to other accelerators for vision Transformers, our design can achieve <inline-formula> <tex-math>$3.3times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$3.7times $ </tex-math></inline-formula> improvements in throughput and energy efficiency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1282-1295"},"PeriodicalIF":5.2,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}