IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Designing Low-Loss Single-Inductor Multiple-I/O (SL-MI/O) CMOS Power Supplies","authors":"Linyuan Cui;Gabriel A. Rincón-Mora","doi":"10.1109/TCSI.2025.3546231","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3546231","url":null,"abstract":"Switched-inductor power supplies are valued for their high efficiency despite the bulkiness of off-chip inductors. When designing compact systems like portable consumer electronics and wireless microsensors, single-inductor topologies are therefore preferred. Specifically, single-inductor multi-input and multi-output (SL-MI/O) power supply designs pose unique challenges that have yet to be fully addressed. This paper aims to provide design guidelines for maximizing efficiency in the design of SL-MI/O systems, especially in the sub-5W domain. To simplify the choice between NFETs and PFETs for the multitude of power switches in SL-MI/Os, which is not straightforward, an intuitive metric called the Favorability Index (F<inline-formula> <tex-math>${}_{mathrm {NP}}$ </tex-math></inline-formula>) is proposed. A new, optimal supply voltage theory is also presented, suggesting that the most efficient voltage to supply power switches’ gates is around twice the threshold voltage (v<inline-formula> <tex-math>${}_{mathrm {T}}$ </tex-math></inline-formula>). The paper also proposes using dynamic selectors in gate drivers. This allows for blocking cross conduction without increasing vSUP drastically, ensuring efficiency. A two-transistor selector is recommended as a simple implementation, and the tradeoffs are discussed. An example topology is designed using guidelines proposed by the paper to demonstrate the design flow and efficiency improvements.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3766-3776"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs From RTL Simulation Bypassing Gate-Level Simulation","authors":"M. B. Rakesh;Pabitra Das;K. R. Sai Pranav;Amit Acharyya","doi":"10.1109/TCSI.2025.3555891","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555891","url":null,"abstract":"This paper proposes an inductive Graph Neural Network (GNN) based methodology for accurate and fast average power estimation of logic-synthesized and RTL-simulated ASIC Design, eliminating gate-level simulation. With the novel variation of inductive GNN architecture, the proposed model propagates the input wires’ toggle rates acquired from RTL simulation through the synthesized design. We only train the proposed model on circuits synthesized from TSMC 65nm technology node but test on the circuits synthesized across TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm technology nodes. We test the inductivity of the proposed model to predict the output wires’ toggle rates of unseen and untrained logic cells of the designs. We compute the proposed methodology’s average power inference throughput (number of cycles inferred per second) for speed comparison. The proposed model does better than state-of-the-art architecture GRANNITE to predict the unseen and untrained logic cell’s toggle rates of the designs across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, showing an average improvement of 6.67%, 8.49%, 9.26%, 7.47% and 6.36%, respectively. The proposed methodology is more accurate than the commercial RTL average power estimation tool and GRANNITE in estimating the average power of circuits across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes by achieving a mean improvement of 24.94%, 16.77%, 17.65%, 29.72%, and 32.84%; 2.75%, 1.1%, 1.81%, 2.59% and 4.49%; respectively. The proposed methodology is 11.07X faster, with an average inference throughput of 1.218kHz, than the commercial gate-level average power estimation tool.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2818-2831"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dual Slope Boosted Relaxation Oscillator With 2.93 μJ/Cycle Energy Efficiency and 0.068% Period Jitter in 180 nm CMOS","authors":"Yongjuan Shi;Xun Liu;Chen Hu;Xiyuan Tang;Junmin Jiang","doi":"10.1109/TCSI.2025.3557560","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557560","url":null,"abstract":"This paper presents a 2MHz relaxation oscillator designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (FIA) is adopted such that 1) the requirement of comparator speed is significantly alleviated and 2) the power consumption of the amplifier is further reduced. The proposed relaxation oscillator was fabricated in a 180nm CMOS process and occupies only 0.1mm² active area. The measurement results with 8 samples show that the average power consumption is <inline-formula> <tex-math>$2.93mu $ </tex-math></inline-formula>J/cycle (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W/MHz) at 1V supply voltage at room temperature. The average standard variation of the period jitter is 345ps, which is 0.068% of 500ns typical oscillation period (<inline-formula> <tex-math>$T_{mathrm {OSC}}$ </tex-math></inline-formula>). The measured temperature coefficient is 128ppm/°C within the 0 to 90°C range, and the voltage variation is 0.74%/0.1V from 0.95V to 1.15V. It scores a high phase noise figure-of-merit of 148dBc/Hz at 10kHz offset frequency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2520-2528"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Inductor Current Ripple Minimization in PV-Fed Modular Multilevel DC-DC Converter With Distributed MPPT Control","authors":"V. Sukanya;G. V. Sumesh;S. J. Lohit Prakash;B. Bijukumar","doi":"10.1109/TCSI.2025.3558367","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558367","url":null,"abstract":"Modular multilevel DC-DC converters find extensive use in power electronics due to their utilization of a single inductor, the potential for serial connection of N number of sub-modules (SMs), and a modular design. Recent research indicates that minimizing ripple in inductor current is feasible by maintaining a fixed interleaving angle of <inline-formula> <tex-math>$frac {100}{N}$ </tex-math></inline-formula> % between the SMs during equal duty ratio operating conditions. This study explores the application of these converters in photovoltaic (PV) systems incorporating individual maximum power point tracking (MPPT) control. In this context, individual MPPT control imposes varied duty ratio conditions on the SMs, arising from differences in the sources of each SM, especially in instances of partial shading condition (PSC). This variability can potentially influence the current ripple within the system. This article conducts a thorough theoretical analysis to derive the optimal interleaving angle criteria for minimizing current ripple under conditions of unequal duty ratios. Additionally, a control strategy is proposed to integrate angle optimization with MPPT control based on the derived conditions. Further, it is observed that operating the converter at this optimal angle leads to a significant reduction in ripple current, by a factor of at least <inline-formula> <tex-math>$frac {1}{N}$ </tex-math></inline-formula>. The MATLAB/PLECS simulations and experimental results verify considerable improvements in ripple reduction compared to the conventional interleaving angle method, both during steady-state and PSC.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4389-4402"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Power-Efficient Active-RC Filter Using Passive Integrator and OTA With Push-Pull Output","authors":"Liangbo Lei;Cong Tao;Zhipeng Chen;Zhiliang Hong;Yumei Huang","doi":"10.1109/TCSI.2025.3554894","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554894","url":null,"abstract":"This paper presents a power-efficient fourth-order, 50-MHz active-RC filter with high dynamic range (DR). Unlike conventional Tow-Thomas biquads, the proposed design employs a passive integrator as the second pole to reduce power consumption, enhance noise performance, and facilitate frequency compensation. The active integrator features a two-stage operational transconductance amplifier (OTA) with a push-pull output, ensuring linearity and reducing the OTA’s gain requirements. Fabricated in standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology, the proposed filter achieves an in-band (IB) input third-order intercept point (IIP3) of +29.9 dBm at 30 MHz and an input-referred IB integrated noise of <inline-formula> <tex-math>$163.8~mu $ </tex-math></inline-formula>VRMS, while consuming 5.4 mW for a 50-MHz bandwidth.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5314-5324"},"PeriodicalIF":5.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient FPGA Implementation of Multi-Channel Pipelined Large FFT Architectures Based on SA-MDF Algorithm","authors":"Tang Hu;Chunling Hao;Xier Wang;Zhiwei Liu;Songnan Ren;Zhiwei Xu;Shiqiang Zhu","doi":"10.1109/TCSI.2025.3547003","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547003","url":null,"abstract":"FPGA implementation of a multi-channel pipelined large FFT architecture is challenging due to its complex inter-channel data scheduling, high-throughput requirement, and resource-constrained hardware. By transforming to 2D-FFT implementation, investigating different binary tree schemes, and exploring various radices, butterflies, as well as data path structures, many hardware architectures have been designed to enhance single-channel large FFT or multi-channel medium-small size FFT performance. These designs fall short in addressing the demands of multi-channel pipelined and large FFT applications. In this article, a self-attention multipath delay feedback (SA-MDF) algorithm is proposed to analyze and identify the most critical bottleneck, then automatically pay attention to improve it, and finally generate the optimal FFT framework by exhaustively exploring the design space. The proposed algorithm alleviates the design difficulties and speeds up the FPGA implementation. Furthermore, an approximate roofline model and a novel binary tree scheme are introduced to further minimize the utilization of on-chip memory. A comprehensive comparison in terms of principles, implementation methods, and optimization effects is conducted when compared with other multi-channel FFT architectures. Experimental results show that the proposed FFT architectures are superior to other FFT implementations in terms of channel count, FFT length, high-throughput data arrangement, and adaptability to diverse hardware platforms.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2189-2201"},"PeriodicalIF":5.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing","authors":"P. J. Zhou;R. C. Ma;Y. C. Chen;Z. T. Liu;C. Y. Liu;L. W. Meng;G. C. Qiao;Y. Liu;Q. Yu;S. G. Hu","doi":"10.1109/TCSI.2025.3557955","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557955","url":null,"abstract":"The transformer model has demonstrated significant capabilities in various intelligent tasks, attracting widespread attention in recent years. However, it involves numerous complex operations, including large-bit-width multiplication, division, matrix transposition, and exponentiation. These require substantial storage and computational resources, making it challenging to deploy on edge devices. This work introduces a neuromorphic transformer architecture with low hardware cost for AI edge computing (AI-EC). At the structural level, it absorbs scaling factors within the self-attention mechanism into weight matrixes, thereby eliminating the division caused by the scaling operation. Additionally, a transposition calculation method is proposed to perform matrix transposition using dedicated memory access strategies and optimized data flow designs, which reduces logic resource overhead and avoids memory access discontinuities. At the computing paradigm level, the architecture employs spike-driven computing, substituting multi-bit multipliers with AND logic for synaptic operations. The paradigm introduces high sparsity to computational data, which is effectively exploited to reduce the computational workload of the architecture. The results indicate that the architecture successfully eliminates high-cost operators and significantly reduces computational expenses. Eventually, this architecture is verified as a prototype using a 28 nm CMOS process library, demonstrating a compact logic area of sub-0.2 mm² and a high energy efficiency of 0.34 pJ/SOP @ 50MHz. This work is expected to promote the application of transformers in edge computing and the development of intelligent edge applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2676-2689"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Power Subthreshold Voltage References for High-Temperature Applications","authors":"Youngwoo Ji;Yuyang Li;Inhee Lee","doi":"10.1109/TCSI.2025.3554367","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554367","url":null,"abstract":"Advanced Internet-of-Things (IoT) devices are increasingly used in high-temperature environments, such as automotive, aerospace, defense, and industrial applications. High-temperature voltage references are crucial for these systems. This paper presents two topologies designed for high-temperature operation. The first topology minimizes design costs by using a replica branch to decouple leakage from the core, reducing its impact on the reference voltage. The second topology optimizes the operating temperature by employing one-stage amplifiers as buffers to handle junction leakage while maintaining body voltage. Both designs are fabricated in a 180 nm CMOS process. The first design supports operation up to <inline-formula> <tex-math>$140~^{circ }$ </tex-math></inline-formula> C with an average temperature coefficient (TC) of 70 ppm/°C, while the second design operates up to <inline-formula> <tex-math>$170~^{circ }$ </tex-math></inline-formula> C with a TC of 64 ppm/°C. The designs also exhibit line sensitivities of 0.46 %/V and 0.31 %/V, PSRRs of –37.8 dB and –38.3 dB at 100 Hz, and power consumption of 111 pW and 136.8 pW at room temperature, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2529-2542"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multi-Stage RC Compensation Technique for Decoupling the Transimpedance and BW: Creating High Speed and Low Noise TIA Designs","authors":"Muhammad Bilal Babar;Gordon W. Roberts","doi":"10.1109/TCSI.2025.3556802","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3556802","url":null,"abstract":"The gain and bandwidth of a shunt-feedback Transimpedance Amplifier (TIA) is limited by a so called transimpedance (TI) limit. This limit dictates the maximum possible value of the feedback resistance (<inline-formula> <tex-math>$R_{F}$ </tex-math></inline-formula>) for a targeted bandwidth. Additionally, the input referred noise of such TIAs is inversely proportional to the <inline-formula> <tex-math>$R_{F}$ </tex-math></inline-formula>, which presents a challenge in simultaneous optimization of bandwidth, noise and transimpedance gain. In this paper, the TI limit is revisited, and a multi-stage RC compensation technique is presented for the design of the open-loop amplifier for a closed-loop shunt-feedback-based TI stage. This paper shows that with the appropriate pole-zero positioning, the DC transimpedance gain can be decoupled from the closed-loop TI bandwidth. This is achieved by placing a zero in the open loop transfer function to reduce the impact of the closed loop dominant pole created by the input capacitance and the RF. As a result, without the need for area consuming inductors, a TI stage is realized which has a transimpedance limit that is larger than the conventionally assumed limit. Additionally, the proposed RC compensation network provides more control over the pole-zero positioning which results in smooth overall frequency response after equalization. This is verified by experimental results which show that the proposed technique achieves a much greater transimpedance gain as compared to that of the conventional limit while reducing the noise and without any significant deterioration of bandwidth. The design has been implemented in a 90 nm BiCMOS process from Global Foundries (GF-9HP). A detailed comparison of the proposed approach is presented with other TIA designs. As per the author’s best knowledge, the proposed design outperforms the state-of-the-art TIA designs in terms of the noise-transimpedance-bandwidth trade-off.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3847-3860"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10962192","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Unified Sampled-Data Small-Signal Model for a Ripple-Based COT Buck Converter With Arbitrary Ripple Injection Network","authors":"Francesco Gabriele;Antonio Carlucci;Davide Lena;Fabio Pareschi;Riccardo Rovatti;Stefano Grivet-Talocia;Gianluca Setti","doi":"10.1109/TCSI.2025.3557278","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557278","url":null,"abstract":"In this paper, we present a novel and unified small-signal modeling technique for Pulse-Width Modulated (PWM) DC-DC Buck converters with Ripple-Based Constant On-Time (RBCOT) control. In fact, despite the spread of RBCOT-based converters in several applications requiring tight dynamic performances and a low architectural complexity, their description through small-signal models is not always as reliable as that of fixed-frequency PWM control architectures, and a general and exact modeling framework is not well established. The proposed methodology is grounded on the DC-DC converter state-space representation and thus, differently from other modeling techniques, it permits to fully characterize the dynamic behavior of generic RBCOT converter topologies with arbitrary complex power stage and ripple injection networks. As a case study, we derive the small-signal model for a Buck converter embedding a widely used ripple injection network in industrial applications. The validity of the theoretical results is confirmed through direct comparison with SIMetrix/SIMPLIS simulations and experimental measurements in practical application scenarios, confirming the accuracy of the model even well beyond the converter switching frequency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2942-2955"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}