IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第6页

DCAP: A Scalable Decoupled-Clustering Annealing Processor for Large-Scale Traveling Salesman Problems DCAP：用于大规模旅行推销员问题的可扩展解耦聚类退火处理器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-02 DOI: 10.1109/TCSI.2024.3449693

Zhanhong Huang;Yang Zhang;Xiangrui Wang;Dong Jiang;Enyi Yao

{"title":"DCAP: A Scalable Decoupled-Clustering Annealing Processor for Large-Scale Traveling Salesman Problems","authors":"Zhanhong Huang;Yang Zhang;Xiangrui Wang;Dong Jiang;Enyi Yao","doi":"10.1109/TCSI.2024.3449693","DOIUrl":"10.1109/TCSI.2024.3449693","url":null,"abstract":"The Traveling Salesman Problem (TSP) is one of the most well-known NP-hard combinatorial optimization problems (COPs). Many social production problems can be effectively represented as instances of TSPs. However, solving large-scale TSPs remains a significant challenge for conventional Von Neumann computers. Many studies have proposed annealing processors to address large-scale COPs, but most of them focus on unconstrained problems, such as the Maxcut problem. In this paper, a scalable decoupled-clustering annealng processor (DCAP) for efficiently handling large-scale TSPs is presented. A decoupled hierarchical clustering algorithm is proposed for higher convergence speed and improved scalability. Several techniques have been developed in hardware to minimize area overhead and processing time, including a modified spin connection topology for the Ising model, an area-efficient random threshold generator, a one-step spin update scheme and a dynamic prediction method. The DCAP prototype is implemented on FPGA with an operating frequency of 125MHz. We tested our design on various TSP instances from the TSPLIB. Results show that our design outperforms the CPU- and GPU-based Neuro-Ising scheme by achieving maximum speedups of \u0000<inline-formula> <tex-math>$780times $ </tex-math></inline-formula>\u0000 and a 42% improvement in accuracy. With multi-chip interconnection, DCAP is able to handle problems of scale up to 85900 cities.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6349-6362"},"PeriodicalIF":5.2,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Node-Based Polar List Decoder With Frame Interleaving and Ensemble Decoding Support 支持帧交错和集合解码的基于节点的极性列表解码器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-02 DOI: 10.1109/TCSI.2024.3443598

Yuqing Ren;Leyu Zhang;Ludovic Damien Blanc;Yifei Shen;Xinwei Li;Alexios Balatsoukas-Stimming;Chuan Zhang;Andreas Burg

{"title":"A Node-Based Polar List Decoder With Frame Interleaving and Ensemble Decoding Support","authors":"Yuqing Ren;Leyu Zhang;Ludovic Damien Blanc;Yifei Shen;Xinwei Li;Alexios Balatsoukas-Stimming;Chuan Zhang;Andreas Burg","doi":"10.1109/TCSI.2024.3443598","DOIUrl":"10.1109/TCSI.2024.3443598","url":null,"abstract":"Node-based successive cancellation list (SCL) decoding has received considerable attention in wireless communications for its significant reduction in decoding latency, particularly with 5G New Radio (NR) polar codes. However, the existing node-based SCL decoders are constrained by sequential processing, leading to complicated and data-dependent computational units that introduce unavoidable stalls, reducing hardware efficiency. In this paper, we present a frame-interleaving hardware architecture for a generalized node-based SCL decoder. By efficiently reusing otherwise idle computational units, two independent frames can be decoded simultaneously, resulting in a significant throughput gain. Based on this new architecture, we further exploit graph ensembles to diversify the decoding space, thus enhancing the error-correcting performance with a limited list size. Two dynamic strategies are proposed to eliminate the residual stalls in the decoding schedule, which eventually results in nearly \u0000<inline-formula> <tex-math>$2 times $ </tex-math></inline-formula>\u0000 throughput compared to the state-of-the-art baseline node-based SCL decoder. To impart the decoder rate flexibility, we develop a novel online instruction generator to identify the generalized nodes and produce instructions on-the-fly. The corresponding 28nm FD-SOI ASIC SCL decoder with a list size of 8 has a core area of 1.28 mm2 and operates at 692 MHz. It is compatible with all 5G NR polar codes and achieves a throughput of 3.34 Gbps and an area efficiency of 2.62 Gbps/mm2 for uplink (1024, 512) codes, which is \u0000<inline-formula> <tex-math>$1.41 times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.69 times $ </tex-math></inline-formula>\u0000 better than the state-of-the-art node-based SCL decoders.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5457-5470"},"PeriodicalIF":5.2,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response 具有双注入控制功能的全 NMOS KY 升压转换器，可实现快速线路和负载瞬态响应

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-02 DOI: 10.1109/TCSI.2024.3446884

Yu-Ting Hung;Chieh-Ju Tsai;Ching-Jan Chen;Chan-Hsuan Hsu;Chun-Yu Hsieh

{"title":"An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response","authors":"Yu-Ting Hung;Chieh-Ju Tsai;Ching-Jan Chen;Chan-Hsuan Hsu;Chun-Yu Hsieh","doi":"10.1109/TCSI.2024.3446884","DOIUrl":"10.1109/TCSI.2024.3446884","url":null,"abstract":"In this paper, a KY-boost converter with double injection control for the mobile devices is presented. The conventional boost converter suffers from several issues, including large output voltage ripples and slow line and load transient responses. A KY-boost converter is a good candidate to overcome the above drawbacks which has buck-like characteristics. A KY boost converter integrated circuit (IC) is proposed in this paper to achieve better line and load transient responses with the smallest chip size compared with the prior arts. A double injection control is proposed in the KY-boost converter to improve line transient response without affecting loop gain and load transient response. Besides, the issues of start-up and larger chip size for KY converter are improved by the all NMOS power stage design with cross-coupled gate driver. The proposed KY-boost converter IC was fabricated with 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process, and the overall chip area is 1.1 mm2 including pads. The measured peak efficiency of this work can achieve 92.95%. When the proposed double injection control is enabled, the output voltage deviation during line transition can be reduced by more than 200% from 80 mV to 36 mV compared with input voltage feedforward control.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5005-5016"},"PeriodicalIF":5.2,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Single-Stage Single-Phase Dual-Output Hybrid Converter 新型单级单相双输出混合转换器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-30 DOI: 10.1109/TCSI.2024.3447837

Shri Prakash Sonkar;Dong-Choon Lee;Honnyong Cha

引用次数: 0

An Ultra-Low Phase Noise Dual-Tank Oscillator Featuring Tank Impedance Scaling 具有槽阻抗缩放功能的超低相位噪声双槽振荡器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-30 DOI: 10.1109/tcsi.2024.3443752

Fariborz Lohrabi Pour, Dong Sam Ha, Amir Nikpaik

引用次数: 0

$DeltaSigma$ Modulators Employing MASH DSM DAC-Based Dual Quantization 采用基于 MASH DSM DAC 的双量化的 $DeltaSigma$ 调制器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-30 DOI: 10.1109/tcsi.2024.3448224

Ahmed Abdelaal, Michael Pietzko, John G. Kauffman, Ankesh Jain, Maurits Ortmanns

引用次数: 0

Finite-Time Asynchronous Switching Control for Fuzzy Markov Jump Systems by Applying Polynomial Membership Functions 应用多项式成员函数实现模糊马尔可夫跳跃系统的有限时间异步切换控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-30 DOI: 10.1109/TCSI.2024.3448629

Yinghong Zhao;Likui Wang;Xiangpeng Xie;Hak-Keung Lam

引用次数: 0

A 4–22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and 28–31 dB Gain Enhanced by the Negative Load Impedance 一款 4-22 GHz 超宽带低噪声放大器，具有 0.8-1.5 dB NF 和 28-31 dB 增益，并通过负负载阻抗得到增强

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-29 DOI: 10.1109/tcsi.2024.3448534

Xiaojie Zhang, Kuisong Wang, Ruiying Gao, Yuying Zhang, Jing Wan, Zhiyong Zhou, Xuming Sun, Xiaoxin Liang

引用次数: 0

Power System Frequency Estimation With Zero Response Time Under Abrupt Transients 突发瞬态下零响应时间的电力系统频率估计

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-29 DOI: 10.1109/tcsi.2024.3447703

Kai Wang, Feiyang Zhong, Jian Song, Zichuan Yu, Lu Tang, Xusheng Tang, Qing Yao

引用次数: 0

A Memcapacitor Biomimetic Circuit Realizing Classical Conditioning and Fear Learning 实现经典条件反射和恐惧学习的记忆电容器仿生电路

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-29 DOI: 10.1109/tcsi.2024.3448235

Junwei Sun, Bairen Chen, Peng Liu, Shiping Wen, Yanfeng Wang

引用次数: 0