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IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

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Switching Loss Model for Fast-Switching GaN HEMT in Half-Bridge Circuit Considering Parasitic Inductance and Temperature Effect 考虑寄生电感和温度效应的半桥电路中快速开关 GaN HEMT 的开关损耗模型
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-28 DOI: 10.1109/TCSI.2024.3480951
Yushan Liu;Jianyu Cao;Xiao Li
{"title":"Switching Loss Model for Fast-Switching GaN HEMT in Half-Bridge Circuit Considering Parasitic Inductance and Temperature Effect","authors":"Yushan Liu;Jianyu Cao;Xiao Li","doi":"10.1109/TCSI.2024.3480951","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3480951","url":null,"abstract":"In power conversion applications utilizing GaN HEMTs at elevated switching frequencies, the predominant source of power loss is attributed to switching, which becomes particularly sensitive to parasitic parameters due to the rapid switching operation. Traditional methods of calculating switching loss have exhibited inconsistencies when applied to designs incorporating GaN HEMTs and various operational conditions. Consequently, there is a pressing need for more precise methods to estimate switching loss in GaN HEMTs. This paper introduces two distinct switching loss calculation models, presented both as empirical formulas and analytical models. These models take into account the influence of critical parasitic inductances and junction temperature. The comparative analysis of these two calculation methods with the experimental results is provided to demonstrate their efficacy. Furthermore, the impact of nonideal factors, such as power loop parasitic inductance, common-source inductance, and junction temperature, is assessed.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6128-6137"},"PeriodicalIF":5.2,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3469775
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3469775","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3469775","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736188","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2024 集成电路与系统国际研讨会--ISICAS 2024》特邀编辑专刊
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3471029
Xinmiao Zhang
{"title":"Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2024","authors":"Xinmiao Zhang","doi":"10.1109/TCSI.2024.3471029","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3471029","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"4899-4899"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736185","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TechRxiv: Share Your Preprint Research with the World! TechRxiv：与世界分享您的预印本研究成果！
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3477149
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSI.2024.3477149","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3477149","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5371-5371"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736148","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Achieving Error-Free Lightweight Authentication With DRAM-Based Physical Unclonable Functions
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3480852
Nico Mexis;Nikolaos Athanasios Anagnostopoulos;Stefan Katzenbeisser;Elif Bilge Kavun;Sara Tehranipoor;Tolga Arul
{"title":"Achieving Error-Free Lightweight Authentication With DRAM-Based Physical Unclonable Functions","authors":"Nico Mexis;Nikolaos Athanasios Anagnostopoulos;Stefan Katzenbeisser;Elif Bilge Kavun;Sara Tehranipoor;Tolga Arul","doi":"10.1109/TCSI.2024.3480852","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3480852","url":null,"abstract":"In this article, we introduce a novel approach to achieving lightweight device authentication through the use of a low-complexity Convolutional Neural Network (CNN). In our work, we improve the False Authentication Rate (FAR) by transforming the standard CNN into a Bayesian CNN (BCNN or BNN). This transformation enables the use of probabilistic modelling techniques, increasing the model’s robustness and its confidence in authentication decisions. Regardless of the model used, clients authenticate with a retention-based Dynamic Random Access Memory Physical Unclonable Function (DRAM PUF) response. Our approach integrates the low computational complexity of the CNN with the intrinsic security characteristics of the DRAM PUF, offering a robust solution for lightweight and secure device authentication.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"637-646"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.1 V-Programmable Metal-Fuse Technology With Current-Mode Programming and Program-Guarantee Technique in 28 nm CMOS Technology
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3447276
Philex Ming-Yan Fan;Chen-An Chen;Chih-Hao Wang;Hsiang-Yu Ko
{"title":"A 1.1 V-Programmable Metal-Fuse Technology With Current-Mode Programming and Program-Guarantee Technique in 28 nm CMOS Technology","authors":"Philex Ming-Yan Fan;Chen-An Chen;Chih-Hao Wang;Hsiang-Yu Ko","doi":"10.1109/TCSI.2024.3447276","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3447276","url":null,"abstract":"The first 1.1V-programmable metal-fuse technology in 28nm CMOS technology is reported in this work. The prototyped 1Kb-memory array featuring a <inline-formula> <tex-math>$12.4mu $ </tex-math></inline-formula>m2 1T1R bit cell adopts the proposed current-mode programming (CMP) scheme. The CMP scheme achieves a record low programming voltage of 1.1V, surpassing the programming voltages (≥1.6V) required by prior metal-fuse CMOS and FinFET technologies. To ensure successful programming, a closed-loop detector (CLD) employing an on-chip hysteresis comparator detects resistance transition in bit cells during programming. Preliminary experiments demonstrate that the proposed CMP scheme along with CLD achieves a 100% of yield after programming 960 bits at room temperature. Under various programming conditions, the combination of CMP and CLD demonstrates programming robustness, with resistance ratios before and after programming equal to and greater than three orders of magnitude. The measured results suggest a promising method for mitigating over-stress issues associated with high programming voltages used in prior art.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"685-693"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE 《电路与系统》期刊--I：常规论文 作者须知
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3469773
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3469773","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3469773","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5372-5372"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter in a Fractional-N Frequency Synthesizer
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3481904
Xu Wang;Michael Peter Kennedy
{"title":"Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter in a Fractional-N Frequency Synthesizer","authors":"Xu Wang;Michael Peter Kennedy","doi":"10.1109/TCSI.2024.3481904","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3481904","url":null,"abstract":"Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance. The resolution of the DTC needs to be sufficiently fine to suppress its own QE below the intrinsic integer-N jitter and, at the same time, sufficiently coarse to limit the DTC’s hardware needs. In this manuscript, we propose optimal strategies to determine the effective dynamic range, number of bits, quantization resolution, and unity delay of the DTC to achieve these goals; the additional jitter power introduced by input-dithered quantization methods to eliminate DTC-quantization-induced spurs is also considered. DTCs parameterized following these strategies can come close to realizing the spur-free integer-N PN with minimum hardware. Behavioral simulations confirm our analysis.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"708-718"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736006","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Privacy-Preserving Federated Reinforcement Learning Method for Multiple Virtual Power Plants Scheduling
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3479427
Ting Yang;Xiangwei Feng;Shaotang Cai;Yuqing Niu;Haibo Pen
{"title":"A Privacy-Preserving Federated Reinforcement Learning Method for Multiple Virtual Power Plants Scheduling","authors":"Ting Yang;Xiangwei Feng;Shaotang Cai;Yuqing Niu;Haibo Pen","doi":"10.1109/TCSI.2024.3479427","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3479427","url":null,"abstract":"The application of federated learning in Virtual Power Plants (VPPs) addresses the data silo issue between VPPs and enhances their ability to cope with nonlinear and stochastic scheduling characteristics, which enables VPPs better accommodate distributed energy resources and flexible loads while participating in frequency regulation services. However, although existing federated learning methods strive to solve privacy protection issues, the plaintext transmission of gradients still exposes sensitive data to the threat of curious power control centers and external inference attacks. Therefore, a privacy-protected horizontal federated reinforcement learning approach for multi-VPP optimal scheduling is proposed in this paper. Firstly, a cost-based global optimization scheduling model for multiple VPPs is constructed, modeling the internal scheduling process of VPPs as a Markov decision process. Then, an improved secure horizontal federated multi-VPP collaborative training method is presented, and local models are trained using the Deep Transformer Q-Network algorithm, with local differential privacy and CKKS homomorphic encryption implemented to ensure privacy protection. Finally, a case study is conducted using frequency regulation ancillary service market data and the IEEE-39 bus system structure. Simulation results show that the proposed approach outperforms similar algorithms, achieving high levels of privacy protection and economic operation for VPPs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1939-1950"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143725103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information IEEE 电路与系统论文集--I：常规论文 出版信息
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-25 DOI: 10.1109/TCSI.2024.3469771
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3469771","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3469771","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736149","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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