IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第10页

Circuit Transfer Matrix: A Novel Approach to Enhancing Circuit Analysis Efficiency by Extending the Transfer Matrix Method for Multibody System 电路传递矩阵：一种扩展多体系统传递矩阵法以提高电路分析效率的新方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2025.3531876

Zhan Jin;Xiao-Ting Rui;Fu-Feng Yang

{"title":"Circuit Transfer Matrix: A Novel Approach to Enhancing Circuit Analysis Efficiency by Extending the Transfer Matrix Method for Multibody System","authors":"Zhan Jin;Xiao-Ting Rui;Fu-Feng Yang","doi":"10.1109/TCSI.2025.3531876","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3531876","url":null,"abstract":"To address the challenge of high computational complexity in large-scale circuit analysis, the Circuit Transfer Matrix Method is proposed, drawing on the strong parallels between electrical and mechanical systems. This method builds upon the Transfer Matrix Method for Multibody Systems, which has seen significant breakthroughs and widespread use in complex mechanical systems, extending its application to circuit analysis. Unlike traditional model-reduction techniques, the circuit transfer matrix method employs the concepts of ‘transfer’ of system state vectors and the ‘assembly’ of transfer matrices, effectively reducing the order of the system’s equations and significantly improving computational efficiency. This reduced-order model allows designers to analyze and synthesize a system’s dynamic behavior within a limited design cycle more efficiently. The text presents the computational workflow of the Circuit Transfer Matrix Method, from the definition of state vectors to the invocation and assembly of transfer matrices, followed by the solution of the transfer equations. The fundamental component transfer matrices are derived upon which the method for deriving the transfer matrices of combined elements is provided, along with a corresponding example. Subsequently, examples are provided to illustrate the detailed computational processes for linear AC analysis, transient analysis of linear chain systems, transient analysis of linear closed-loop systems, and transient analysis of general nonlinear systems. The accuracy of the algorithm is validated by comparisons with methods based on SPICE. Finally, a comparison of the algorithm speed with SPICE reveals that SPICE has an asymptotic time complexity of <inline-formula> <tex-math>$O(n^{3})$ </tex-math></inline-formula>, while the Circuit Transfer Matrix Method has a complexity of only <inline-formula> <tex-math>$O(n)$ </tex-math></inline-formula>, significantly enhancing computational efficiency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2804-2817"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

First Demonstration of Power-Linear Regulator for Thermo-Optic Phase Tuning 热光相位调谐功率线性调节器的首次演示

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2025.3549722

Yuhang Wang;Da Ming;Xiaofei Chen;Bing Li;Min Tan

{"title":"First Demonstration of Power-Linear Regulator for Thermo-Optic Phase Tuning","authors":"Yuhang Wang;Da Ming;Xiaofei Chen;Bing Li;Min Tan","doi":"10.1109/TCSI.2025.3549722","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549722","url":null,"abstract":"This paper presents a power-linear regulator (PLR) using a voltage-squaring feedback loop designed for linear thermo-optic tuning. Nonlinear phase tuning occurs when conventional digital-to-analog converters (DACs) or low-dropout regulators (LDOs) are used to drive the thermo-optic phase shifter since the introduced phase change is proportional to the square of the voltage. The nonlinear phase tuning introduces the distortion and non-uniform resolution which degrades the system performance. We propose a PLR to achieve linear thermo-optic phase tuning, where the phase change is proportional to the input voltage. By adopting a voltage-squaring feedback loop, the output voltage is proportional to the square-root of the input voltage under fixed resistive heater and a linear mapping between the input voltage and phase change is established. This design is fabricated in a standard CMOS 65 nm process with an active area of 0.014 mm2. Under 2.5 V supply voltage, the proposed design achieves an input range of <inline-formula> <tex-math>$0sim 1$ </tex-math></inline-formula> V and corresponding output range of <inline-formula> <tex-math>$0sim 2$ </tex-math></inline-formula> V. The maximum delivered power is up to 40 mW while driving a <inline-formula> <tex-math>$100~Omega $ </tex-math></inline-formula> load. The measured power linearity error is <inline-formula> <tex-math>$3.5~%$ </tex-math></inline-formula>. Additionally, the design demonstrates rapid transient behavior under a <inline-formula> <tex-math>$100~Omega $ </tex-math></inline-formula> load, with <inline-formula> <tex-math>$0.2~mu $ </tex-math></inline-formula>s rise time and <inline-formula> <tex-math>$0.7~mu $ </tex-math></inline-formula>s fall time between 0 mW output power and 40 mW output power. The line regulation is 6 mV/V under <inline-formula> <tex-math>$100~Omega $ </tex-math></inline-formula> load. To the best of our knowledge, it is the first PLR demonstrated in the literature.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2039-2047"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-Harmonic EMI Reduction Optimization of Spread Spectrum in Multiple-RBW Environment 多rbw环境下扩频多谐波EMI抑制优化

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2025.3549360

Francesco Gabriele;Fabio Pareschi;Davide Lena;Maria Rosa Borghi;Riccardo Rovatti;Gianluca Setti

{"title":"Multi-Harmonic EMI Reduction Optimization of Spread Spectrum in Multiple-RBW Environment","authors":"Francesco Gabriele;Fabio Pareschi;Davide Lena;Maria Rosa Borghi;Riccardo Rovatti;Gianluca Setti","doi":"10.1109/TCSI.2025.3549360","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549360","url":null,"abstract":"We investigate here both from a theoretical and practical point of view the problem of optimizing EMI reduction by means of spread spectrum clocking when lower harmonics need to be analyzed with a smaller RBW, and higher harmonics with a larger one. This situation is indeed a trade-off, where a designer can trade performance in terms of EMI reduction for lower harmonics with that achieved for higher harmonics. Two approaches are considered and analyzed. The first trade-off, denoted as Single Triangular Modulation, consists in the standard and commonly adopted triangular based spreading, where the role of the parameters is investigated with the aim of optimizing EMI reduction both in the lower part and the upper part of the spectrum. The second one, denoted as Double Triangular Modulation, is inspired by a recent Application Note and it is much more complex from an implementation point of view, being based on two simultaneous triangular modulations with different parameters. The comparison shows very similar performance, so that the adoption of the more complex approach results questionable.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3488-3497"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Time and Energy-Efficient Asynchronous Hybrid-Searching Auto Frequency Calibration for a 3.2 GHz Phase-Locked Loop 3.2 GHz锁相环的一种省时节能异步混合搜索自频校准方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2025.3547024

Zijie Wang;Fanxun Cai;Lianbo Wu;Hui Zhang;Weisheng Zhao

{"title":"A Time and Energy-Efficient Asynchronous Hybrid-Searching Auto Frequency Calibration for a 3.2 GHz Phase-Locked Loop","authors":"Zijie Wang;Fanxun Cai;Lianbo Wu;Hui Zhang;Weisheng Zhao","doi":"10.1109/TCSI.2025.3547024","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547024","url":null,"abstract":"Wide-band wireless system-on-chip demands phase-locked loops(PLL) designed with multi-band voltage controlled oscillators (VCO), which requires auto frequency calibration (AFC) for frequency presetting. This paper proposes a high-speed energy-efficient integrated AFC with asynchronous hybrid searching technique. The asynchronous architecture breaks the minimum limit of search time, while the hybrid method overcomes nonmonotonic variation of frequency errors in binary search. A true single-phase clock (TSPC)-based RF digital counter further accelerates AFC by directly quantizing the VCO output frequency. In this paper, a 3.2GHz PLL is presented utilizing the high-speed AFC to achieve fast locking performance. Implemented in 28nm CMOS technology, the proposed AFC for a 7-bit VCO achieves a calibration time of 0.88-<inline-formula> <tex-math>$4.74boldsymbol {mu }$ </tex-math></inline-formula>s across available tuning range, while the time of each step reaches 120ns level. With the aid of AFC, the prototype PLL reaches settle in less than <inline-formula> <tex-math>$11.8boldsymbol {mu }$ </tex-math></inline-formula>s, while achieving 318.2fs integrated jitter and -64.3dBc reference spur. The Figure-of-Merit (FoM) of the 3.2GHz PLL achieves -239.66dB for <inline-formula> <tex-math>$text {FoM}_{text {jitter}}$ </tex-math></inline-formula>, and -186.16dB for <inline-formula> <tex-math>$text {FoM}_{text {T}_{text {S}}}$ </tex-math></inline-formula>.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5409-5421"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks Bayes2IMC：基于贝叶斯二值神经网络的内存计算

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2025.3543065

Prabodh Katti;Clement Ruah;Osvaldo Simeone;Bashir M. Al-Hashimi;Bipin Rajendran

{"title":"Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks","authors":"Prabodh Katti;Clement Ruah;Osvaldo Simeone;Bashir M. Al-Hashimi;Bipin Rajendran","doi":"10.1109/TCSI.2025.3543065","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3543065","url":null,"abstract":"Bayesian Neural Networks (BNNs) generate an ensemble of possible models by treating model weights as random variables. This enables them to provide superior estimates of decision uncertainty. However, implementing Bayesian inference in hardware is resource-intensive, as it requires noise sources to generate the desired model weights. In this work, we introduce Bayes2IMC, an in-memory computing (IMC) architecture designed for binary BNNs that leverages the stochasticity inherent to nanoscale devices. Our novel design, based on Phase-Change Memory (PCM) crossbar arrays eliminates the necessity for Analog-to-Digital Converter (ADC) within the array, significantly improving power and area efficiency. Hardware-software co-optimized corrections are introduced to reduce device-induced accuracy variations across deployments on hardware, as well as to mitigate the effect of conductance drift of PCM devices. We validate the effectiveness of our approach on the CIFAR-10 dataset with a VGGBinaryConnect model containing 14 million parameters, achieving accuracy metrics comparable to ideal software implementations. We also present a complete core architecture, and compare its projected power, performance, and area efficiency against an equivalent SRAM baseline, showing a 3.8 to <inline-formula> <tex-math>$9.6 times $ </tex-math></inline-formula> improvement in total efficiency (in GOPS/W/mm2) and a 2.2 to <inline-formula> <tex-math>$5.6 times $ </tex-math></inline-formula> improvement in power efficiency (in GOPS/W). In addition, the projected hardware performance of Bayes2IMC surpasses most memristive BNN architectures reported in the literature, achieving up to 20% higher power efficiency compared to the state-of-the-art.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5422-5435"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Structure-Reconfigurable Wide Gain Series Resonant Converter for On-Board Charger 用于车载充电器的结构可重构宽增益串联谐振变换器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2024.3505271

Deyu Wang;Xianpeng Chen;Qinglin Zhao;Zbigniew Kaczmarczyk

{"title":"Structure-Reconfigurable Wide Gain Series Resonant Converter for On-Board Charger","authors":"Deyu Wang;Xianpeng Chen;Qinglin Zhao;Zbigniew Kaczmarczyk","doi":"10.1109/TCSI.2024.3505271","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3505271","url":null,"abstract":"In this article, a structure-reconfigurable series resonant DC-DC converter is proposed for a wide gain on-board charger application. The proposed converter consists of a dual-bridge structure on the primary side which can realize 0.5 to 1 voltage gain by using a reconfigurable half/full bridge structure, and a hybrid rectifier on the secondary side which can realize 1 to infinite voltage gain by replacing two diodes with active switches. Moreover, the proposed converter employs a control scheme based on fixed frequency PWM, with the operating frequency being identical to the series resonant frequency. Accordingly, magnetizing inductance of the transformer is independent of the converter gain characteristics, which simplifies the consideration of the resonance parameters design. In addition, soft switching can be realized during the entire charging process, and high efficiency can be achieved. To avoid the voltage spike and current impact in the transition between two operation modes, a unified switching modulation strategy is applied to achieve a smooth transition and improve the control stability. Finally, a 2.5 kW prototype with an output voltage range of 200V - 500 V is established and tested to verify the effectiveness and feasibility of the proposed converter.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1951-1961"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Topkima-Former: Low-Energy, Low-Latency Inference for Transformers Using Top-k In-Memory ADC Topkima-Former：基于Top-k内存ADC的变压器低能量、低延迟推理

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-18 DOI: 10.1109/TCSI.2025.3549060

Shuai Dong;Junyi Yang;Xiaoqi Peng;Hongyang Shang;Ye Ke;Xiaofeng Yang;Hongjie Liu;Arindam Basu

{"title":"Topkima-Former: Low-Energy, Low-Latency Inference for Transformers Using Top-k In-Memory ADC","authors":"Shuai Dong;Junyi Yang;Xiaoqi Peng;Hongyang Shang;Ye Ke;Xiaofeng Yang;Hongjie Liu;Arindam Basu","doi":"10.1109/TCSI.2025.3549060","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549060","url":null,"abstract":"Transformer has emerged as a leading architecture in neural language processing (NLP) and computer vision (CV). However, the extensive use of nonlinear operations, like softmax, poses a performance bottleneck during transformer inference and comprises up to 40% of the total latency. Hence, we propose innovations at the circuit, algorithm and architecture levels to accelerate the transformer. At the circuit level, we propose Topkima—combining top-<italic>k activation selection with in-memory ADC (IMA) to implement efficient softmax without any sorting overhead. Only the <italic>k largest activations are sent to softmax calculation block, reducing the huge computational cost of softmax. At the algorithmic level, a modified training scheme utilizes top-<italic>k activations only during the forward pass, combined with a sub-top-<italic>k method to address the crossbar size limitation by aggregating each sub-top-<italic>k values as global top-<italic>k. At the architecture level, we introduce a fine pipeline for efficiently scheduling data flows and an improved scale-free technique for removing scaling cost. The combined system, dubbed Topkima-Former, enhances <inline-formula> <tex-math>$1.8times -84times $ </tex-math></inline-formula> speedup and <inline-formula> <tex-math>$1.2times -36times $ </tex-math></inline-formula> energy efficiency (EE) over prior In-memory computing (IMC) accelerators. Compared to a conventional softmax macro and a digital top-<italic>k (Dtopk) softmax macro, our proposed Topkima softmax macro achieves about <inline-formula> <tex-math>$15times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> faster speed respectively. Experimental evaluations demonstrate minimal (0.42% to 1.60%) accuracy loss for different models in both vision and NLP tasks.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2509-2519"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology 撤回通知：不稳定多智能体系统可达成一致性的鲁棒性裕度：定向网络拓扑上的输出一致性协议

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-17 DOI: 10.1109/TCSI.2025.3539893

Qi Mao;Shi Li;Guobao Liu;Liqian Dou;Bailing Tian;Qun Zong

{"title":"Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology","authors":"Qi Mao;Shi Li;Guobao Liu;Liqian Dou;Bailing Tian;Qun Zong","doi":"10.1109/TCSI.2025.3539893","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3539893","url":null,"abstract":"In this article, we deliver analytical expressions to characterize the attainable consensusability of a linear unstable multi-agent system (MAS). The considered MAS undergoes uncertainty variations and non-minimum phase dynamics, whose interaction topology is delineated by a communication network with a directed spanning tree. Our primary objective is to compute the maximal robustness consensus margins, which can clearly describe how communication network connectivity, the control protocols, and the system's dynamics exert influences on allowable robustness consensus in the framework of output feedback control. Towards this aim, we resolve the robust consensus problem along the spirit of the gain and phase margin problems, which amounts to handling two constrained optimization problems over feasible regions based on the stability analysis theorem of the MAS characteristic polynomials. We finally formulate explicit conditions and analytical expressions of achieved robustness consensus margins, wherein the results show the restrictions of the agent's unstable pole, non-minimum phase zero, and network connectedness on the robustly achieved gain and phase consensus margins.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2481-2481"},"PeriodicalIF":5.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10929757","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 94.2% Peak Efficiency Full Duty Range Flying-Capacitor Sharing Dynamic Four-Path Hybrid Converter With Reduced Body Diode Loss Technique 采用低体二极管损耗技术的94.2%峰值效率全占空范围飞电容共享动态四路混合变换器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-15 DOI: 10.1109/TCSI.2025.3567507

Chi-Lung Lee;Yu-Tse Shih;Yi-Ching Chiu;Chieh-Sheng Hung;Rong-Bin Guo;Ke-Horng Chen;Kuo-Lin Zheng;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai

引用次数: 0

Impedance Circuit Model of Voltage Source Converter With DC-Link Voltage Control Dynamics 具有直流链路电压控制动力学的电压源变换器阻抗电路模型

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-03-14 DOI: 10.1109/TCSI.2025.3548907

Zhen Wang;Peng Cheng;Hao Pan;Limin Jia

{"title":"Impedance Circuit Model of Voltage Source Converter With DC-Link Voltage Control Dynamics","authors":"Zhen Wang;Peng Cheng;Hao Pan;Limin Jia","doi":"10.1109/TCSI.2025.3548907","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3548907","url":null,"abstract":"The impedance circuit model maps the control algorithms into the circuit topology of voltage source converters (VSCs). By analyzing discrete circuit elements, the model provides clear physical insight for the oscillation mechanisms triggered by the control dynamics. However, previous studies do not consider the outer-loop control and reactive power. To enhance the generality, this paper integrates the DC-link voltage control (DVC) loop into the impedance circuit model and thoroughly considers the non-unity power factor operating conditions. In this model, DVC dynamics is mapped as two equivalent impedances in the AC circuit, and interaction between the inner and outer loops is visualized by the interconnection of impedances. The analysis indicates that the perturbation of DVC dynamics on grid-connected current introduces the negative resistance effect at low-power levels. Moreover, the effect of reactive power on impedance circuit is mapped as a coupled current source linking the d-axis and q-axis circuits. As the inductive-reactive power increases, self-excited oscillations occur in the coupled source. According to the stability constraints of the coupled sources, a strict design method for the control parameters is proposed. Experimental results verify the effectiveness of the proposed model.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2970-2983"},"PeriodicalIF":5.2,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0