IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第10页

A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-04 DOI: 10.1109/TCSI.2024.3458057

F. de Los Santos-Prieto;F. J. Rubio-Barbero;R. Castro-Lopez;E. Roca;F. V. Fernandez

{"title":"A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs","authors":"F. de Los Santos-Prieto;F. J. Rubio-Barbero;R. Castro-Lopez;E. Roca;F. V. Fernandez","doi":"10.1109/TCSI.2024.3458057","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3458057","url":null,"abstract":"Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"661-670"},"PeriodicalIF":5.2,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Single-Switch High Step-Up DC-DC Converter With High-Voltage Conversion Ratio

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-04 DOI: 10.1109/TCSI.2024.3468372

Yu-En Wu;Sin-Cheng Huang;Che-Ming Chang

引用次数: 0

MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-04 DOI: 10.1109/TCSI.2024.3469928

Adou Sangbone Assoa;Ashwin Bhat;Sigang Ryu;Arijit Raychowdhury

{"title":"MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation","authors":"Adou Sangbone Assoa;Ashwin Bhat;Sigang Ryu;Arijit Raychowdhury","doi":"10.1109/TCSI.2024.3469928","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3469928","url":null,"abstract":"Massive MIMO systems are promising for wireless communications beyond 5G, but scalable Direction-of-Arrival (DOA) estimation in these systems is challenging due to the increasing number of required antennas. Existing solutions, model-based or data-driven (typically using neural networks), face scalability issues with the growing antenna array size. To address this issue, we propose a hybrid system that makes the overall approach scalable. In the front-end, we employ a modular distributed approach namely, the method of sparse linear inverse to compute a proxy spectrum from the sampled covariance matrix of the antenna subarrays. The proxy drives a fixed lightweight back-end which consists of a 1-dimensional Convolution Neural Network (1D-CNN) and a simplified peak extraction. The input proxy dimension being independent of the antenna count makes the neural network input invariant of the array size, enabling it to handle multiple array sizes without requiring any modification of the neural network structure. To reduce the computation of the covariance matrix and proxy spectrum, we employ a system of subarrays with Nearest-Neighbor communication. The proposed approach was implemented on a Xilinx ZCU102 FPGA targeting 100 MHz frequency for 8 to 256-element arrays. We achieve below 1 ms processing time for an array of 256 antennas while requiring significantly less computation than both model-based and data-driven approaches for large antenna arrays.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"941-952"},"PeriodicalIF":5.2,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sequential Bayesian Inference and Monte-Carlo Sampling Using Memristor Stochasticity 利用忆阻器随机性进行序列贝叶斯推理和蒙特卡洛采样

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-03 DOI: 10.1109/TCSI.2024.3470318

Adil Malik;Christos Papavassiliou

引用次数: 0

A Compact Broadband Voltage-Combined Doherty Power Amplifier With Shorted Transmission Line for 5G Millimeter-Wave 用于 5G 毫米波的带短路传输线的紧凑型宽带电压组合多赫蒂功率放大器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-02 DOI: 10.1109/TCSI.2024.3415010

Jiawen Chen;Haoshen Zhu;Jingye Zhang;Quan Xue

{"title":"A Compact Broadband Voltage-Combined Doherty Power Amplifier With Shorted Transmission Line for 5G Millimeter-Wave","authors":"Jiawen Chen;Haoshen Zhu;Jingye Zhang;Quan Xue","doi":"10.1109/TCSI.2024.3415010","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3415010","url":null,"abstract":"This article presents a CMOS voltage-combined Doherty power amplifier (PA) based on a broadband compact load modulation network (LMN) for fifth-generation (5G) millimeter-wave (mm-wave) mobile communication applications. By analyzing the frequency response of different types of Doherty power combiner, a novel voltage-combined Doherty LMN with shorted TL and corresponding design procedure are proposed to achieve broadband power back-off (PBO) bandwidth and compact footprint. A compact quadrature hybrid coupler without lumped capacitor is also devised to generate wideband quadrature signals. To improve PBO efficiency, an envelope detector is adopted to produce adaptive DC bias for auxiliary path. For the proof of concept, a dual-driver Doherty PA is implemented in 65-nm bulk CMOS technology with a chip size of 0.42 mm2 including all pads. The PA achieves a 3-dB small-signal \u0000<inline-formula> <tex-math>$S_{21}$ </tex-math></inline-formula>\u0000 bandwidth from 21.1 to 30.4 GHz and a 1-dB saturated output power (\u0000<inline-formula> <tex-math>$P_{text {sat}}$ </tex-math></inline-formula>\u0000) bandwidth from 24 to 30 GHz. The measured \u0000<inline-formula> <tex-math>$P_{text {sat}}$ </tex-math></inline-formula>\u0000, output 1-dB compression point (\u0000<inline-formula> <tex-math>$OP_{text {1dB}}$ </tex-math></inline-formula>\u0000), peak power-added efficiency (PAE) and PAE at 6dB-PBO are 20.0 dBm, 19.1 dBm, 24.6% and 20.0% at 27 GHz, respectively. For modulation measurements, the proposed PA under 64-quadrature-amplitude-modulated (64-QAM) signal at a data rate of 0.6/2.4 Gb/s achieves average output power (\u0000<inline-formula> <tex-math>$P_{text {avg}}$ </tex-math></inline-formula>\u0000) of 11.5/4.8 dBm and average drain efficiency of 14.1%/3.9% with −25/−24.5 dB of error vector magnitude (EVM) and −29/−25.6 dBc of adjacent channel leakage ratio (ACLR) at 28 GHz, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6190-6202"},"PeriodicalIF":5.2,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-01 DOI: 10.1109/TCSI.2024.3460265

引用次数: 0

A Dynamic Capacitance Matching (DCM)-Based Current Response Algorithm for Signal Line RC Network 基于动态电容匹配的信号线RC网络电流响应算法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-01 DOI: 10.1109/TCSI.2024.3463708

Zhoujie Wu;Cai Luo;Zhong Guan

{"title":"A Dynamic Capacitance Matching (DCM)-Based Current Response Algorithm for Signal Line RC Network","authors":"Zhoujie Wu;Cai Luo;Zhong Guan","doi":"10.1109/TCSI.2024.3463708","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3463708","url":null,"abstract":"This paper proposes a dynamic capacitance matching (DCM)-based RC current response algorithm for calculating the current waveform of a signal line without performing transistor level SPICE simulation. Specifically, unlike previous methods such as current source model, driver linear representation, waveform functional fitting or equivalent load capacitance, our algorithm does not rely on fixed reduced model of standard-cell driver or RC load. Instead, it approaches the current waveform dynamically by computing current responses of the target driver for various load scenarios. Besides, we creatively use symbolic expression to combine the y-parameter of RC network with the pre-characterized driver library in order to perform capacitance matching and simulate current waveform by considering the Miller and over/undershoot effects. Our algorithm is experimentally verified on 40nm CMOS technology and has been adopted by latest commercial tool for different nodes (from 180nm to 3nm). Experimental results show that our algorithm has only about 1% error compared with SPICE golden results while the runtime is improved by 50 to 200 times, which demonstrates overwhelming capability in calculating timing, power and electromigration of signal lines.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5804-5813"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE 《电路与系统》期刊--I：常规论文作者须知

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-01 DOI: 10.1109/TCSI.2024.3460263

引用次数: 0

CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-01 DOI: 10.1109/TCSI.2024.3466217

Yao Qin;Mingyu Wang;Jiahua Yan;Tao Lu;Zhiyi Yu

{"title":"CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications","authors":"Yao Qin;Mingyu Wang;Jiahua Yan;Tao Lu;Zhiyi Yu","doi":"10.1109/TCSI.2024.3466217","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3466217","url":null,"abstract":"Large-scale general matrix multiplications (LMMs) are the key bottlenecks in various computation domains such as Transformer applications. However, it is a challenge to perform LMMs efficiently on traditional multi/many-core processor systems due to the large amount of memory access and the tight dependence of data transmission. By analyzing the aforementioned problems, we propose a computing in network-on-chip paradigm to perform LMMs by mitigating the performance losses caused by limited on-chip cache resources and memory bandwidth. Specifically, we propose a co-design of computable network-on-chip and the last-level cache method in tiled many-core architectures, which can reconstruct the redundant cache capacity as computable input buffer to balance the demands of computing, storage, and communication for the running LMM applications. Furthermore, a data-aware thread execution mechanism is also proposed to maximize the computational efficiency of thread streams in computable network. At the software level, memory-friendly matrix partitioning strategy, hybrid routing method and programming model are designed to bridge the gap between application demands and mismatched hardware/software interfaces. Experimental evaluations demonstrate that this proposed work achieves a computational latency reduction of 45% compared to the state-of-the-art GPU architecture, and the inference performance is improved by <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> of the GPT network.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1256-1268"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact On-Chip mm-wave Reconfigurable Wideband Filtering Switch in 28-nm Bulk CMOS for Integrated Sensing and Communication System Applications 紧凑型片上毫米波可重构宽带滤波开关在28纳米体CMOS集成传感和通信系统的应用

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-10-01 DOI: 10.1109/TCSI.2024.3464734

Hui-Yang Li;Jin-Xu Xu;Xiu Yin Zhang

{"title":"Compact On-Chip mm-wave Reconfigurable Wideband Filtering Switch in 28-nm Bulk CMOS for Integrated Sensing and Communication System Applications","authors":"Hui-Yang Li;Jin-Xu Xu;Xiu Yin Zhang","doi":"10.1109/TCSI.2024.3464734","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3464734","url":null,"abstract":"In this paper, we propose a compact wideband on-chip millimeter-wave (mm-wave) reconfigurable wideband filtering switch in 28-nm bulk CMOS technology. A dual-mode LC resonator loaded with transistors is used to achieve wideband filtering responses with a transmission zero at the lower frequency band. The resonant frequency of the resonator and the location of the transmission zero can be conveniently tuned to reconfigure the passband and stopband frequencies by turning on and off the transistor. Moreover, the passband can also be switched on and off, enabling the single-pole single-throw filtering switch circuit function. In this way, the proposed mm-wave reconfigurable filtering switch is applicable to the integrated sensing and communication (ISAC) system, where image rejection in communication operation and a wide bandwidth (or high resolution) in sensing operation are both required. Furthermore, to meet the applications in the ISAC systems with different architectures, extension designs of the proposed reconfigurable filtering switch with the impedance conversion function, high-order responses, balanced-to-unbalanced transition, and differential input/output ports are presented in detailed. For demonstration, the wideband reconfigurable filtering switch has been fabricated. The core circuit has a very compact size of \u0000<inline-formula> <tex-math>$0.205times 0.140$ </tex-math></inline-formula>\u0000 mm2. Experimental results show that the passband can be reconfigured between 20-55 GHz and 37-44 GHz, with a rejection >17 dB for sensing operation and >12 dB image-band rejection for communication operation, respectively. High off-state isolation of better than 24.8 dB is also achieved.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"125-134"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0