IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第10页

Dynamical Analysis and Fixed-Time Synchronization for Secure Communication of Hidden Multiscroll Memristive Chaotic System 隐藏式多卷膜混沌系统安全通信的动态分析与固定时间同步化

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-05 DOI: 10.1109/TCSI.2024.3434551

Qiang Lai;Yijin Liu;Luigi Fortuna

{"title":"Dynamical Analysis and Fixed-Time Synchronization for Secure Communication of Hidden Multiscroll Memristive Chaotic System","authors":"Qiang Lai;Yijin Liu;Luigi Fortuna","doi":"10.1109/TCSI.2024.3434551","DOIUrl":"10.1109/TCSI.2024.3434551","url":null,"abstract":"In view of the superiority of memristors in strengthening dynamical complexity and the significant application potiential of multiscroll chaos, this paper attempts to introduce two memristors with scalable memductances into simple seed chaotic system for designing multiscroll memristive chaotic system (MMCS). The designed MMCS yields hidden grid multiscroll chaotic attractors with any number of scrolls expanding along with the internal variables of memristors. By varying the parameters, the multiscroll attractors can be broken into coexisting attractors with different numbers and scrolls dependent on parameters, and their oscillation amplitudes can be increased (or decreased) without changing the chaotic features. Dynamical analysis and circuit implementation are given to reveal the complexity and feasibility of the MMCS. The fixed-time synchronization (FxTS) is studied by using adaptive controller and the sufficient condition for FxTS is established via Lyapunov stability theory (LST). A multilevel secure communication scheme based on the FxTS of MMCS is designed and the experimental tests on the image, audio and data secure communication verify its effectiveness, which to some extent shows the application availability of MMCS.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4665-4675"},"PeriodicalIF":5.2,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Complexity Soft-Output Massive MIMO Detector With Near-Optimum Performance 性能接近最优的低复杂度软输出大规模多输入多输出检测器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-05 DOI: 10.1109/tcsi.2024.3435361

Jinjie Hu, Suwen Song, Zhongfeng Wang

引用次数: 0

Power and Frequency Intrinsic Channels on gem5 gem5 上的功率和频率固有通道

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-05 DOI: 10.1109/tcsi.2024.3435841

Lilian Bossuet, Carlos Andres Lara-Nino

引用次数: 0

An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition 基于相角分配的无电网电压传感器三相 PWM 整流器开路故障诊断方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-05 DOI: 10.1109/TCSI.2024.3434683

Chunjie Li;Jianing Hu;Mingwei Zhao;Wei Zeng

{"title":"An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition","authors":"Chunjie Li;Jianing Hu;Mingwei Zhao;Wei Zeng","doi":"10.1109/TCSI.2024.3434683","DOIUrl":"10.1109/TCSI.2024.3434683","url":null,"abstract":"In order to accurately locate the open-circuit fault of power tube for three-phase PWM rectifier under the grid-voltage sensorless control strategy, an open-circuit fault diagnosis algorithm based on phase angle partitions of the current and voltage is proposed. To improve dynamic response for the system, predictive current control is implemented. The real-time change rate of the grid-current phase angle is utilized to determine whether a fault occurs. Based on the zero value platform in the grid-side distortion current generated by open-circuit faults, the corresponding phase angles for the grid current and the grid voltage are partitioned to locate the fault tubes. In a grid voltage sensorless control system, the grid voltage information obtained by the voltage observer and phase-locked loop can be susceptible to distortion or interference. To enhance the accuracy of phase-locked angle, a double generalized second-order integrator is used. The proposed open-circuit fault detection method can realize rapid diagnosis and location for single and double power tubes under grid-voltage sensorless predictive current control. Finally, experimental results are presented to verify the feasibility of the diagnosis method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5318-5328"},"PeriodicalIF":5.2,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC 利用片上可配置电流转向测温 DAC 改进线性度的过程变化感知内存计算

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-02 DOI: 10.1109/TCSI.2024.3422883

Prasanna Kumar Saragada;Bishnu Prasad Das

{"title":"Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC","authors":"Prasanna Kumar Saragada;Bishnu Prasad Das","doi":"10.1109/TCSI.2024.3422883","DOIUrl":"10.1109/TCSI.2024.3422883","url":null,"abstract":"The in-memory computation (IMC) is a potential technique to improve the speed and energy efficiency of data-intensive designs. However, the scalability of IMC to large systems is hindered by the non-linearities of analog multiply-and-accumulate (MAC) operations and process variation, which impacts the precision of high bit-width MAC operations. In this paper, we present an IMC architecture that is capable of performing multi-bit MAC operations with improved speed, linearity, and computational accuracy. To improve the speed/linearity of the IMC-MAC operations, the image and weight data are applied by using the pulse amplitude modulation (PAM) and thermometric techniques, respectively. Although the PAM technique improves the speed of the IMC-MAC operations, it has linearity issues that need to be addressed. Based on the detailed linearity analysis of the IMC-MAC circuit, we proposed two approaches to improve the linearity and the signal margin (SM) of the IMC architecture. The proposed configurable current steering thermometric digital-to-analog converter (CST-DAC) array is employed to provide the PAM signals with various dynamic ranges and non-linear gaps that are required to improve the linearity/SM. The proposed combined PAM and thermometric IMC (PT-IMC) architecture is designed and fabricated in the TSMC 180-nm CMOS process. The post-silicon calibration of the design point mitigates the process-variation issues and provides the maximum SM (close to the simulation results). Furthermore, the proposed PT-IMC architecture performs MNIST/CIFAR-10 data set classification with an accuracy of 98%/88%. In addition, the PT-IMC architecture achieves a peak throughput of 12.41 GOPS, a normalized energy efficiency of 30.64 TOPS/W, a normalized figure-of-merit (FOM) of 3039, a loss in the SM of 8.3% with respect to the ideal SM, and a computational error of 0.41%.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4586-4596"},"PeriodicalIF":5.2,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141884506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Time-to-Voltage Converter-Based MPPT With 440 μs Online Tracking Time, 99.7% Tracking Efficiency for a Battery-Less Harvesting Front-End With Cold-Startup and Over-Voltage Protection 一种基于时间电压转换器的 MPPT，在线跟踪时间为 440 美元，跟踪效率为 99.7%，适用于具有冷启动和过压保护功能的无电池集电前端

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-02 DOI: 10.1109/TCSI.2024.3435533

Aditi Chakraborty;Ashis Maity

{"title":"A Time-to-Voltage Converter-Based MPPT With 440 μs Online Tracking Time, 99.7% Tracking Efficiency for a Battery-Less Harvesting Front-End With Cold-Startup and Over-Voltage Protection","authors":"Aditi Chakraborty;Ashis Maity","doi":"10.1109/TCSI.2024.3435533","DOIUrl":"10.1109/TCSI.2024.3435533","url":null,"abstract":"This paper introduces a time-to-voltage converter-based maximum power point tracking (TVCB-MPPT) for harvesting photovoltaic energy into a super-capacitor using a single solar cell. In the proposed design, a time-to-voltage converter is used to achieve a fast and accurate tracking of the maximum power point (MPP) without using a time-averaging/time-integrating function as used in the conventional time-based MPPT design. Moreover, with the continuous monitoring of the MPP, the proposed converter responds immediately and maximizes the extracted energy under varying irradiance conditions as compared to the conventional intermittent MPPT topologies. The addition of the cold-start operation and the over-voltage protection increase the robustness and energy-autonomy of the overall system. The proposed TVCB-MPPT converter is fabricated in a 180 nm CMOS process. In the measured result, a fast online MPP tracking time of \u0000<inline-formula> <tex-math>$440~mu $ </tex-math></inline-formula>\u0000s is observed with an initial tracking time of 4.8 ms. It also shows a peak tracking efficiency of 99.7% with a power conversion efficiency >87% in the entire input power range.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4499-4511"},"PeriodicalIF":5.2,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141884509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link 用于串行链路的高能效电阻器-电感器混合型全双工收发器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-02 DOI: 10.1109/tcsi.2024.3435530

V. K. Surya, Suraj Kumar Prusty, Bibhu Datta Sahoo, Nijwm Wary

引用次数: 0

NOMA System Performance Improvement Using Chaos and Deep Learning 利用混沌和深度学习提高 NOMA 系统性能

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-02 DOI: 10.1109/tcsi.2024.3431470

Hui-Ping Yin, Hai-Peng Ren

引用次数: 0

CorTile: A Scalable Neuromorphic Processing Core for Cortical Simulation With Hybrid-Mode Router and TCAM CorTile：利用混合模式路由器和 TCAM 进行大脑皮层仿真的可扩展神经形态处理核心

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-02 DOI: 10.1109/tcsi.2024.3431036

Fanxi Yang, Yuhan He, Jinqiao Yang, Anqin Xiao, Lufei Fan, Ning Ma, Li-Rong Zheng, Zhuo Zou

引用次数: 0

LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography LiCryptor：用于轻量级密码学的高速紧凑型多粒度可重构加速器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-01 DOI: 10.1109/TCSI.2024.3434686

Hoai Luan Pham;Vu Trung Duong Le;Van Duy Tran;Tuan Hai Vu;Yasuhiko Nakashima

{"title":"LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography","authors":"Hoai Luan Pham;Vu Trung Duong Le;Van Duy Tran;Tuan Hai Vu;Yasuhiko Nakashima","doi":"10.1109/TCSI.2024.3434686","DOIUrl":"10.1109/TCSI.2024.3434686","url":null,"abstract":"Emerging modern internet-of-things (IoT) systems require hardware development to support multiple 8/32/64-bit lightweight cryptographic (LWC) algorithms with high speed and energy efficiency to ensure diverse security requirements. Accordingly, a coarse-grained reconfigurable array (CGRA) is considered the most effective architecture for achieving high speed, low power, and high flexibility for implementing LWC algorithms. However, existing CGRA designs for cryptography focus only on improvements to outdated 8/32-bit algorithms, suffer from large area requirements, and have long compilation times. To address these issues, this paper proposes a new CGRA-based accelerator named LiCryptor to support various 8/32/64-bit LWC algorithms with high speed and small area. Three innovative ideas are proposed to enable LiCryptor to achieve these goals: a compact multi-grained processing element array (M-PEA), a shared 8/32/64-bit arithmetic logic unit (ALU), and an assembly-like inline directive (AID) mapping method. The LiCryptor has been successfully implemented and verified on the Xilinx ZCU102 FPGA. Real-time performance evaluation across various LWC algorithms on FPGA shows that LiCryptor is 1.33 to 4 times better in execution time and 3.4 to 153 times better in power-delay products (PDP) compared to today’s most powerful CPUs. Notably, evaluation of AID mapping on the ARM Cortex-A53 CPU of the ZCU102 FPGA shows that its compilation time is less than 1.5 ms for most LWC algorithms, at least 2,333 times faster than CFG mapping in current CGRAs. Moreover, experimental results on 45nm ASIC technology show that the LiCryptor significantly outperforms existing CGRAs and other reconfigurable designs in terms of throughput and area efficiency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4624-4637"},"PeriodicalIF":5.2,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141884581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0