IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Phase Modulated Bistatic Radar With an Analog Correlator: A Systematic Study","authors":"Wen Zhou;Yahya Tousi","doi":"10.1109/TCSI.2025.3529678","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3529678","url":null,"abstract":"This work presents a phase-modulated radar based on an analog correlator. We demonstrate a novel radar architecture that combines the energy efficiency of analog processing and the accuracy and flexibility of digital processing while avoiding their respective pitfalls. We introduce the proposed analog correlator, describe its theory of operation, and develop a numerical model to analyze and predict the output and the detection sensitivity. Next, we perform a thorough architectural analysis and present system-level simulations of the proposed structure. Finally, based on this investigation we derive circuit requirements and perform extensive radar simulations characterizing the performance of the implemented analog correlator. There is agreement between theoretical derivations, expected performance from system-level models, and the resulting performance from circuit-level time-domain simulations, demonstrating the feasibility of the proposed scheme for high-performance pulse-modulated radars.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1204-1217"},"PeriodicalIF":5.2,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spiketrum: An FPGA-Based Implementation of a Neuromorphic Cochlea","authors":"Mhd Anas Alsakkal;Jayawan Wijekoon","doi":"10.1109/TCSI.2025.3526585","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526585","url":null,"abstract":"This paper presents a novel FPGA-based neuromorphic cochlea, leveraging the general-purpose spike-coding algorithm, Spiketrum. The focus of this study is on the development and characterization of this cochlea model, which excels in transforming audio vibrations into biologically realistic auditory spike trains. These spike trains are designed to withstand neural fluctuations and spike losses while accurately encapsulating the spatial and precise temporal characteristics of audio, along with the intensity of incoming vibrations. Noteworthy features include the ability to generate real-time spike trains with minimal information loss and the capacity to reconstruct original signals. This fine-tuning capability allows users to optimize spike rates, achieving an optimal balance between output quality and power consumption. Furthermore, the integration of a feedback system into Spiketrum enables selective amplification of specific features while attenuating others, facilitating adaptive power consumption based on application requirements. The hardware implementation supports both spike-based and non-spike-based processors, making it versatile for various computing systems. The cochlea’s ability to encode diverse sensory information, extending beyond sound waveforms, positions it as a promising sensory input for current and future spike-based intelligent computing systems, offering compact and real-time spike train generation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1648-1656"},"PeriodicalIF":5.2,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler","authors":"Yoichi Iizuka;Akihide Maezono;Wataru Saito;Kazuhiko Takami;Fukashi Morishita","doi":"10.1109/TCSI.2025.3528426","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3528426","url":null,"abstract":"This document presents a CMOS image sensor (CIS) with a high-speed single slope ADC(SS-ADC) that has a novel high-speed counter and can reduce temporal noise in a wide range of frequency components by enabling correlated multiple sampling (CMS) and digital correlated double sampling (DCDS) at high frame rates. The test chip was fabricated in 55nm process and has 8.3M pixels. The counter was confirmed to operate at a frequency equivalent to 5.36GHz. It uses a circuit and dedicated counter code that suppresses differential non-linearity (DNL) deterioration due to faster counter speeds. When CMS is performed 4 times at 30 frames per second (fps), the random noise is 187uVrms, which is a 31% improvement in noise compared to when CMS is not performed.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1105-1113"},"PeriodicalIF":5.2,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Distributed Hybrid-Triggered Observer-Based Secondary Control of Multi-Bus DC Microgrids Over Directed Networks","authors":"Xuecheng Li;Changbin Hu;Shanna Luo;Heng Lu;Zhengguo Piao;Liuming Jing","doi":"10.1109/TCSI.2024.3523339","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3523339","url":null,"abstract":"The secondary control (SC) of DC Microgrids (MGs) exhibits fast control dynamics as a consequence of low system inertia, leading to substantial communication, networked sensor sampling, and computational load. The existing pure event-triggered (ETed) or self-triggered (STed) SC approaches for DC MGs struggle to optimize communication, sampling, and computation efficiency concurrently. To address this issue, this study introduces a novel distributed hybrid-triggered (HTed) dynamic-consensus-observer-based SC tailored for average voltage restoration and load current sharing in general multi-bus DC MGs over directed networks. Firstly, the dynamic model of SC over directed networks is established. Subsequently, a Lyapunov stability condition is derived to guarantee the stability of the proposed HTed SC. The HTed SC integrates ETed communication with STed sampling and computation, eliminating the need for continuous networked sensor sampling and trigger condition monitoring present in traditional ETed SCs while also reducing the trigger conservativeness of conventional STed SCs. Consequently, the HTed SC achieves a lower communication, sampling, and computation rate. Experimental tests conducted using an MG prototype and a real communication network validated the efficacy of the proposed methodology.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2467-2480"},"PeriodicalIF":5.2,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive Neural Control of Superheated Steam System in Ultra-Supercritical Units With Output Constraints Based on Disturbance Observer","authors":"Zhongrui Zhou;Juan Zhang;Yingchun Wang;Dongsheng Yang;Zeyi Liu","doi":"10.1109/TCSI.2025.3530995","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3530995","url":null,"abstract":"For the superheated steam temperature control system, an optimized disturbance observer and output-constrained control algorithm have been designed. Initially, the original system with output constraints is transformed into a system without any state constraints, suitable for backstepping design, through state transformation. Then, based on the concept of negative gradient optimization, a gain iterative disturbance observer is constructed, which dynamically improves the control accuracy of the system compared to a constant gain disturbance observer. Finally, an adaptive neural control scheme based on the gain iterative disturbance observer is proposed, proving that all output states are constrained within predefined bounds, and all closed-loop signals are semi-globally uniformly bounded. The effectiveness of the proposed scheme is demonstrated through a simulation example of the superheated steam temperature system.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2701-2711"},"PeriodicalIF":5.2,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece","authors":"Haochen Zhang;Xinyuan Qiao;Jing Tian;Suwen Song;Zhongfeng Wang","doi":"10.1109/TCSI.2025.3528119","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3528119","url":null,"abstract":"Classic McEliece, with a remarkably stable security level, has been selected as one of the four key-establishment algorithms in the fourth-round evaluation of the post-quantum cryptography (PQC) standardization process of national institute of standards and technology (NIST). However, its memory-intensive and time-consuming key generation poses an obstacle to widespread use. In this paper, we propose a fast hardware implementation of the key generation incorporating several architectural optimizations. For the Gaussian elimination, we optimize the scheduling of computing resources and the memory access process and present a high-performance and flexible systemizer with multiple low fan-out systolic arrays. Besides, an algorithmic-level parallelized design for entry generation and Gaussian elimination is proposed to reduce the redundant computation time. A compact entry generator with a multi-level feedback mechanism and a 2-D high-speed FFT module facilitates continuous streaming the generated entries into the systemizer.FPGA implementation results show that our designs for the key generation improve time-area efficiency by 11.9% to 43.2% compared to the state-of-the-arts. Moreover, compared to the hardware implementations for the key generation of the other two quasi-cyclic code-based PQC algorithms, ours for Classic McEliece based on the random code achieves close to or better results in several metrics.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1321-1331"},"PeriodicalIF":5.2,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency","authors":"Chao Wang;Zhongkui Zhang;Xiaoyang Xu;Xianzeng Guo;Qihang Gao;Zhaohao Wang;Weisheng Zhao","doi":"10.1109/TCSI.2024.3519745","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519745","url":null,"abstract":"Spin-orbit torque magnetic random-access memory (SOT-MRAM), which exhibits sub-nanosecond write speed and high endurance, is a promising candidate for the future high-level cache. Nevertheless, SOT-MRAM faces challenge in meeting the high read performance requirements of cache applications due to the limited ON/OFF ratio. Consequently, extensive investigation has been conducted into robust complementary bit-cell (CBC) designs based on SOT-MRAM. However, previous designs suffer from significant technology feasibility, area and performance issues. In this paper, the feasibility and performance of the existing complementary write schemes are analyzed, and optimized U-type and toggle spin torque (TST) schemes with practicality and conciseness are presented. The previous CBC designs are evaluated and optimized in terms of circuit and layout, while the 1-word-line-3-bit-line (1WL3BL) CBC designs with both U-type and TST schemes are proposed, which can reduce the bit-cell area by 24.64%-27.54% and improve the write and read performance. In comparison to the conventional CBC design, the proposed 1WL3BL CBC design can reduce the write energy and read latency by up to 36.91% and 21.93%, respectively. Furthermore, the proposed low-voltage read scheme demonstrates the capability to enhance the read performance and conserve the read energy under the aggressive read-related process parameters.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2327-2340"},"PeriodicalIF":5.2,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Over-the-Air Linearization of Phased Array Transmitters Affected by Load Modulation","authors":"Joel Fernandez;Lauri Anttila;Koen Buisman;Mikko Heino;Christian Fager;Thomas Eriksson;Mikko Valkama","doi":"10.1109/TCSI.2025.3527701","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3527701","url":null,"abstract":"Unlocking the potential of millimeter-wave (mmWave) phased array systems demands robust nonlinear transmitter modeling and digital pre-distortion (DPD) techniques. In this article, we present a novel behavioral modeling approach and the corresponding linearization solution for beamforming antenna arrays comprising multiple and mutually interacting nonlinear power amplifier (PA) units. Our non-recursive transmitter model simplifies numerical evaluations across diverse phased array/multiple-input multiple-output (MIMO) configurations under crosstalk-induced load modulation. We introduce a novel, nonlinear forward model parameter identification algorithm tailored for crosstalk-prone array systems and applicable in arbitrary MIMO transmitter configurations, enabling precise modeling and characterization using over-the-air (OTA) observations. Furthermore, we propose an offline direct learning architecture based DPD method, harnessing the estimated nonlinear array forward model and specific beam-sweeping procedure, for linearizing phased arrays under severe load modulation. Numerical assessments across various scenarios demonstrate superior performance, while physical validation on a measurement test bench reinforces our methodology’s real-world applicability. Overall, this work paves the way for advanced nonlinear array transmitter optimization and linearization, vital for next-generation wireless communication networks.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2366-2379"},"PeriodicalIF":5.2,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10843841","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Pixel Noise in Dynamic Vision Sensors","authors":"Donghwan Seo;Jung-Geun Kim;Injune Yeo;Hyunkeun Lee;Byung-Geun Lee","doi":"10.1109/TCSI.2025.3526965","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526965","url":null,"abstract":"To date, pixel noise in a dynamic vision sensor (DVS) has not been accurately analyzed in the literature, and its optimization has been performed empirically. This paper presents a theoretical analysis of the DVS pixel noise. The mean-squared noise voltage at the pixel output from each noise source in a pixel is mathematically derived and verified based on simulations and measurements. A design method to determine the pixel bias currents for a given photocurrent is also presented based on the noise analysis to improve noise performance while maintaining pixel latency. A prototype DVS chip was fabricated in a 110 nm complementary metal-oxide-semiconductor image sensor process and tested under various light and pixel bias conditions. It is shown that the proposed noise analysis and design method successfully predicted the noise performance of the DVS chip.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1081-1092"},"PeriodicalIF":5.2,"publicationDate":"2025-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Coding Unit Depth Identification Using Texture and Multiple Deep Learning Architectures","authors":"Hari Pattimi;Kota Naga Srinivasarao Batta;Polamarasetty Praveen Kumar;Ramakrishna S. S. Nuvvula;Baseem Khan;Aanchal Verma;R. K. Saket","doi":"10.1109/TCSI.2025.3526636","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526636","url":null,"abstract":"High-Efficiency Video Coding (HEVC), often known as H.265, is a new video coding standard that offers substantially better compression efficiency than the previous standard, H.264 while maintaining the same video quality. In HEVC, the quadtree partition method divides Coding Tree Units (CTUs) into Coding Units (CUs). This coding unit partition is recursive and increases computational complexity because it is dependent on rate-distortion optimization (RDO). In this paper, we propose a texture and deep learning-based system, that initiates the CU partition by the calculation of the CU texture attributes. Coding units are classified into three categories based on texturing properties. Class 1 represents mostly homogeneous regions, Class 2 mostly non-homogeneous regions, and Class 3 other regions. Only class 3 blocks are sent through the deep learning architecture. As a result, the total number of blocks partitioned by the deep learning architecture is lowered. We also proposed three distinct deep learning-based architectures in our system for coding unit partitioning, which eliminates the need for rate-distortion optimization and thereby decreases computational complexity. The input to our proposed texture and deep learning-based system is an image of size <inline-formula> <tex-math>$64times 64$ </tex-math></inline-formula> (CTU), while the output is a <inline-formula> <tex-math>$1times 16$ </tex-math></inline-formula> vector representing the depths of the coding tree unit. Simulation results demonstrate the effectiveness of our proposed system. Compared to existing models, our proposed CU-CNN, CU-MobileNet, and CU-Resnet have reduced the encoding time of CU partitions by 68.41%, 75.77%, and 88.08% respectively. In addition, the results demonstrated that the proposed system with the CU-MobileNet model is appropriate for mobile or lightweight applications, while the CU-Resnet model works well for time-critical or high-speed applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1372-1382"},"PeriodicalIF":5.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}