IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2025.3569470","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3569470","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11018066","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2025.3569472","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3569472","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2984-2984"},"PeriodicalIF":5.2,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11018073","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2025.3569474","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3569474","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11018077","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Generalized Multilevel Code-Shifted Differential Chaos Shift Keying Modulation System","authors":"Shou-Yi Li;Hua Yang;Guo-Ping Jiang","doi":"10.1109/TCSI.2025.3571716","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3571716","url":null,"abstract":"To achieve a high data rate while maintaining a low peak to average power ratio (PAPR), a novel generalized multi-level code-shifted differential chaos shift keying modulation system is proposed. In this system, both the reference and multiple data-bearing signals transmit data bits through code index modulations performed on the same set of Walsh codes, leading to enhanced utilization of indices and increased data rate. In addition, each data-bearing signal transmits one extra bit using differential chaos shift keying modulation. To mitigate high PAPR, discrete cosine spreading codes are employed to distinguish between the reference and data-carrying signals. Two receiver configurations are designed to balance low complexity and improved bit error rate performance. Bit error rate performances are analyzed and simulated under the additive white Gaussian noise and multipath Rayleigh fading channels. Finally, comparisons are made between the proposed and other CS-DCSK-based systems, which illustrates that our system can offer an increased data rate and superior bit error rate performance, along with a reduced PAPR.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 11","pages":"7225-7237"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2025.3550689","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550689","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945525","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prescribed Performance-Based Distributed Predefined Time Control for DC Microgrid Clusters","authors":"Mohamed Zaery;Syed Muhammad Amrr;Mohammad Ali;S. M. Suhail Hussain;Mohammad A. Abido","doi":"10.1109/TCSI.2025.3553702","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553702","url":null,"abstract":"Interconnecting DC microgrids (MGs) into a cluster enhances renewable energy utilization and improves power supply reliability by enabling power flow between them. Effective management of DC MG clusters requires a control system designed for rapid response to fluctuating renewable source behavior and load demands. Traditional control methods lack the ability to pre-specify desired system performance, including convergence time and transient/steady-state behavior. Therefore, this work explores a prescribed performance function-based predefined time (PPF-PDT) control for optimizing the power dispatch of interconnected DC MGs according to the user-assigned preplanned desired performance. This scheme comprises secondary and tertiary control layers to handle the optimal operation for individual MGs and interconnected MGs, respectively, using a dual-layer sparse cyber network. In each MG, the secondary control matches the incremental costs of all distributed generation units while stabilizing the MG’s average voltage to the assigned voltage level within an adjustable predefined settling time independent of initial states. Adopting PPF significantly enhances transient and steady-state behavior, ensuring the tracking errors remain within desired performance limits. Additionally, distributed tertiary controllers across multiple MGs adjust their voltage references to optimize the exchanged power among them within a user-assigned tunable settling time. A thorough Lyapunov analysis verifies the stability of the proposed control algorithm within the predefined time and confines the tracking errors within acceptable bounds. Extensive simulation and experimental studies confirm the feasibility of the control strategy under various conditions.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"6262-6275"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2025.3550691","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550691","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1975-1975"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945524","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2025.3550693","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550693","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient and Reconfigurable Post-Quantum Crypto-Processor for SPHINCS+","authors":"Tianze Huang;Jiahao Lu;Dongsheng Liu;Zhixiang Luo;Chi Cheng;Aobo Li;Lei Chen;Shuo Yang;Jiaming Zhang;Xiang Li","doi":"10.1109/TCSI.2025.3544341","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3544341","url":null,"abstract":"SPHINCS+ is the sole hash-based digital signature scheme among the selected post-quantum cryptography (PQC) in 2022. This algorithm possesses the ability to resist attacks from both classical and quantum computers. Due to the extensive computations and different data widths for various parameters, its hardware implementation faces the weakness of long operation time, large area requirement, and low flexibility. This paper presents an efficient and reconfigurable SPHINCS+ processor. The proposed on-the-fly WOTS+ public key generation scheme with unified chain address generator accelerated the most time-consuming operations. This optimization achieves efficient resource utilization. A security switch mechanism resolves the bit misalignment among different data widths with resource reduction. Finally, we introduce a grouped subtree and segmented signature streaming scheme. They reduce the memory to 16k bytes. The processor consumes 29410 LUTs, 14090 FFs, 4 BRAMs on Artix-7 FPGA and achieves <inline-formula> <tex-math>$1.04times/2.41times $ </tex-math></inline-formula> ATPs (area-time-product) optimizations in Sign/Verify with the advantage of supporting all security levels of SPHINCS+.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2252-2262"},"PeriodicalIF":5.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation","authors":"Meng Guo;Qi Wu;Chuanning Wang;Yangcan Zhou;Shaowei Wang;Chuan Zhang;Zhongfeng Wang;Jun Lin","doi":"10.1109/TCSI.2025.3547319","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547319","url":null,"abstract":"Channel estimation (CE) is a critical component in the massive multi-input multi-output (MIMO) communication systems. Compared with conventional CE algorithms, deep learning (DL)-based approach becomes a promising alternative, due to its capability of offering enhanced performance and robustness across diverse scenarios. However, efficient DL-based CE algorithms have two key properties that make them challenging for implementation in existing architectures at the edge side: the diversity of deep neural networks (DNNs) and CE strategies, and the involvements of multiple computation-intensive tasks that compass conventional signal processing, artificial intelligence (AI) inference, and online learning. To address these challenges, a domain-specific processor based on an extended RISC-V instruction set architecture (ISA) is proposed to perform these DL-based CE algorithms. First, a dedicated RISC-V ISA extension is developed to support all essential operations required by a DL-based CE algorithm, such as matrix inversion, in a flexible manner. Building on the customized ISA extension, a highly adaptable and scalable RISC-V processor is developed, featuring scalar and vector posit arithmetic units to alleviate high computational and memory demands of DNNs during both inference and training phase. Additionally, a coarse-grained matrix accelerator is integrated to expedite various matrix operations ensuring high throughput. In this way, both high flexibility and computational efficiency are achieved. Finally, our processor is implemented on a TSMC 28-nm technology. Implementation results show that the processor achieves a speedup of <inline-formula> <tex-math>$5.16sim 6.80times $ </tex-math></inline-formula> for all matrix operations compared with the state-of-the-art work. Moreover, the proposed processor provides an area efficiency improvement of <inline-formula> <tex-math>$1.61times $ </tex-math></inline-formula> and an energy efficiency enhancement of <inline-formula> <tex-math>$6.6sim 15.4times $ </tex-math></inline-formula> compared to the open-source vector processor Ara. Notably, this work is the first RISC-V domain-specific processor tailored for diverse DL-based CE algorithms.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2380-2393"},"PeriodicalIF":5.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}