IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

IBLFs-Based Closed-Loop Dynamics Modeling and Neural Control for Time-Varying Full State Constrained Unknown Nonlinear Systems via Deterministic Learning 基于iblfs的时变全状态约束未知非线性系统闭环动力学建模与神经网络控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-09-23 DOI: 10.1109/TCSI.2025.3607965

Qinchen Yang;Weitian He;Yuchen Liang;Fukai Zhang;Chenguang Yang;Cong Wang

{"title":"IBLFs-Based Closed-Loop Dynamics Modeling and Neural Control for Time-Varying Full State Constrained Unknown Nonlinear Systems via Deterministic Learning","authors":"Qinchen Yang;Weitian He;Yuchen Liang;Fukai Zhang;Chenguang Yang;Cong Wang","doi":"10.1109/TCSI.2025.3607965","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3607965","url":null,"abstract":"Learning is central to intelligent control, particularly in real-world scenarios with complex time-varying constraints. This paper proposes an adaptive neural network-based control method for unknown nonlinear systems subject to fully time-varying state constraints. Unlike conventional barrier Lyapunov functions (BLFs) methods, the proposed approach directly enforces state constraints through time-varying integral barrier Lyapunov functions (IBLFs). An adaptive neural controller is developed to ensure all system states remain within their prescribed time-varying bounds while achieving tracking convergence. However, the use of IBLF leads to a highly intricate closed-loop error subsystem and unknown system dynamics, posing challenges for theoretical learning analysis. To address this, we provide a rigorous proof of the closed-loop neural network (NN) learning process under IBLF constraints, ensuring accurate approximation of unknown dynamics. Furthermore, the learned constraint-related dynamics are encapsulated in constant NNs, enabling a knowledge-based learning controller. By addressing closed-loop learning under time-varying IBLF constraints, the proposed method achieves high-performance control and advances dynamic learning and control theory for constrained nonlinear systems.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2900-2912"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147571065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Game-Based Human-Swarm Shared Formation Control Authority Transfer of Manned–Unmanned Aerial Team 基于博弈的人-群共享编队控制权限转移

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-09-22 DOI: 10.1109/TCSI.2025.3609736

Mengzhen Huo;Haibin Duan

引用次数: 0

A 3.3 Gb/s/mm2 Area-Efficient Non-Binary LDPC Decoder Using Column-Layered Processing 3.3 Gb/s/mm2非二进制LDPC解码器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-11-18 DOI: 10.1109/TCSI.2025.3632901

Jeongwon Choe;Youngjoo Lee

{"title":"A 3.3 Gb/s/mm2 Area-Efficient Non-Binary LDPC Decoder Using Column-Layered Processing","authors":"Jeongwon Choe;Youngjoo Lee","doi":"10.1109/TCSI.2025.3632901","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3632901","url":null,"abstract":"Non-binary low-density parity-check (NB-LDPC) codes are a prominent class of error-correction codes, offering superior error-correcting performance compared to their binary counterparts. However, previous NB-LDPC decoders suffer from high processing complexity and significant memory overhead when supporting high-order Galois fields and long codeword lengths. To address these challenges, the proposed decoder leverages the trellis min-max algorithm and adopts a column-layered decoding schedule with on-the-fly message computation to reduce memory requirements. Additionally, the proposed column-layered algorithm shares up-to-date information among columns, enhancing the convergence speed of the baseline design. Considering the structure of high-rate NB-LDPC codes, we introduce multi-column processing with an optimized banked memory architecture while minimizing parallel processing overhead through submodule optimization. Fabricated using a 28-nm CMOS technology, the prototype 4KB 0.9-rate decoder achieves a 1.42-fold improvement in area efficiency compared to state-of-the-art designs. While the proposed design is motivated by the requirements of storage applications, its modular organization and scalable parallelism also allow adaptation to diverse domains such as wireless and optical communications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2847-2857"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147571047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Offline Deep Reinforcement Learning-Based Home Energy Management Systems With Heterogeneous EV Charging Load Models 基于离线深度强化学习的异构电动汽车充电负荷模型家庭能源管理系统

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-09-05 DOI: 10.1109/TCSI.2025.3600455

Luolin Xiong;Yang Tang;Kankar Bhattacharya;Mo-Yuen Chow;Feng Qian

{"title":"Offline Deep Reinforcement Learning-Based Home Energy Management Systems With Heterogeneous EV Charging Load Models","authors":"Luolin Xiong;Yang Tang;Kankar Bhattacharya;Mo-Yuen Chow;Feng Qian","doi":"10.1109/TCSI.2025.3600455","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3600455","url":null,"abstract":"With increasing penetration of Electric Vehicles (EVs) into the transportation system and smart electricity grid, there is a growing need for integrating them into Home Energy Management Systems (HEMS). This integration within HEMS introduces dynamic user behaviors and time-varying charging demand, thus posing challenges for the HEMS. To mitigate these challenges, this paper proposes a charging model for heterogeneous EVs that covers the range of Plug-in Hybrid EVs (PHEVs), Range-Extender EVs (REEVs) and Battery EVs (BEVs) with/without heat pumps. The proposed heterogeneous EV charging model considers weather conditions, estimated mileage and driver’s experience to describe the dynamic charging demand and the anxiety level influencing their behavior. To optimize the HEMS operation, minimizing the energy cost and ensuring comfort, this paper introduces an offline Deep Reinforcement Learning (DRL) algorithm which learns directly from pre-collected datasets, avoiding the cost and safety issues associated with continuous real-world interactions. The algorithm incorporates the Huber loss and a Q-quantile estimator to mitigate performance degradation from dataset anomalies such as data noise, sensor failure and human error, resulting in more robust HEMS optimization strategies. Experimental results demonstrate the method’s effectiveness in reducing total costs and analyze the performance of household devices with two different electricity rates.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2927-2937"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147570562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Direct 24/48 V-to-1 V Dual-Phase Hybrid DC–DC Converter With VCF Self-Balancing 带VCF自平衡的直接24/48 V- 1v双相混合DC-DC变换器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-12-18 DOI: 10.1109/TCSI.2025.3627903

Yinglyu Xiong;Xun Liu;Ka Nang Leung

{"title":"A Direct 24/48 V-to-1 V Dual-Phase Hybrid DC–DC Converter With VCF Self-Balancing","authors":"Yinglyu Xiong;Xun Liu;Ka Nang Leung","doi":"10.1109/TCSI.2025.3627903","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3627903","url":null,"abstract":"This article presents a dual-phase hybrid dc—dc converter (DPHC) for the applications of high voltage conversion ratio and high output current delivery. The power stage topology evolved from the tri-state double step-down (DSD) topology by inserting a single additional power switch and a flying capacitor. Unlike conventional multi-phase converters that require equal inductor current sharing among all phases, the proposed converter allows intentionally unequal current distribution, which reduces current stress on specific components and improves overall efficiency. Additionally, all the flying capacitor voltages (<inline-formula> <tex-math>$V_{{CF}}$ </tex-math></inline-formula>) of the proposed DPHC are self-balanced during steady-state operation, cutting down the requirement for the circuit design for <inline-formula> <tex-math>$V_{CF}$ </tex-math></inline-formula> calibration. The proposed DPHC retains the characteristics of some other existing multi-level multi-phase hybrid topologies with fewer components. A PCB prototype is built to verify the performance of the proposed DPHC. Experimental results show that the peak efficiencies of the proposed DPHC are 94.6% and 91.1% respectively for the voltage conversion of 24 V/48 V to 1 V.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2999-3012"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147571046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low Complexity High Speed Channel Estimation for OTFS on System on Chip 片上系统OTFS的低复杂度高速信道估计

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-11-19 DOI: 10.1109/TCSI.2025.3632906

Sai Kumar Dora;Sumit J. Darak;Himanshu B. Mishra

{"title":"Low Complexity High Speed Channel Estimation for OTFS on System on Chip","authors":"Sai Kumar Dora;Sumit J. Darak;Himanshu B. Mishra","doi":"10.1109/TCSI.2025.3632906","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3632906","url":null,"abstract":"This work presents a novel, low-complexity hardware implementation of the Two-Choice Hard Thresholding Pursuit (TCHTP) algorithm for sparse channel estimation (CE) in the delay-Doppler (DD) domain, specifically designed for Orthogonal Time Frequency Space (OTFS) modulation. Unlike prior compressed sensing methods, the proposed approach does not require prior knowledge of channel sparsity or statistics, making it highly suitable for real-world, high-mobility scenarios. We formulate the CE problem in a sparse framework and develop a hardware-friendly variant of TCHTP that jointly estimates channel coefficients and their DD positions. To reduce complexity in the coefficient estimation stage involving the inverse operation, we explore and implement three matrix decomposition strategies—singular value decomposition (SVD), QR decomposition, and a novel hybrid QR+SVD approach—on a system-on-chip platform using hardware-software co-design. The proposed hybrid architecture achieves up to 70.6% memory savings, 42.4% reduction in DSP usage, and a <inline-formula> <tex-math>$132times $ </tex-math></inline-formula> speedup over the conventional design, while maintaining BER performance. Additionally, it achieves 10% lower power consumption and delivers an <inline-formula> <tex-math>$84.2times $ </tex-math></inline-formula> increase in end-to-end physical layer throughput.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2858-2871"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147570565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 6–33-GHz Half-Nanosecond True-Time Delay Line With Gain Compensation for Wideband Large-Scale Antenna Array 宽带大型天线阵列6 - 33 ghz半纳秒增益补偿实时延迟线

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-10-13 DOI: 10.1109/TCSI.2025.3617017

Peigen Yu;Dixian Zhao

{"title":"A 6–33-GHz Half-Nanosecond True-Time Delay Line With Gain Compensation for Wideband Large-Scale Antenna Array","authors":"Peigen Yu;Dixian Zhao","doi":"10.1109/TCSI.2025.3617017","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3617017","url":null,"abstract":"This article presents a path-selecting true-time delay (TTD) circuit for wideband large-scale antenna arrays. An in-depth system-level analysis of wideband arrays is conducted to demonstrate the advantage of hybrid array system steered by both phase shifters and TTDs. The corresponding TTD design requirements are derived to enable proper operation of such arrays. The proposed T-coil peaking amplifiers are incorporated to compensate for the steep frequency-scaling losses introduced by the large number of delay lines, thereby ensuring a flat gain across an ultra-wide bandwidth. A detailed design methodology for the T-coil network is presented, and multi-coil coupled floorplan are utilized to facilitate compact layout implementation. In the high-delay path, field-reinforced floorplan are adopted for artificial transmission lines to enhance area efficiency, while in the low-delay path, distributed loss-shaping networks are introduced to mitigate loss variations across different delay states. The proposed TTD circuit is fabricated in 65-nm bulk CMOS, occupying a compact chip area of 1.6<inline-formula> <tex-math>$mathrm {times }$ </tex-math></inline-formula>1.2 mm<sup>2</sup>. It achieves a measured delay range of half a nanosecond with 6-bit resolution across 6–33 GHz. The losses from delay lines are effectively compensated, yielding in an overall gain of 0 dB. The combination of wide bandwidth, large delay range, and low loss makes the proposed TTD circuit well-suited for wideband applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2835-2846"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147570567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Inverse Reinforcement Learning-Based Asynchronous Filtering for SMIB Power Systems With Stochastic Mode Switching 基于逆强化学习的随机模式切换SMIB电力系统异步滤波

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-11-10 DOI: 10.1109/TCSI.2025.3627956

Weidi Cheng;Hai Wang;Yanyan Yin;Shuping He;Ho Ching Iu

{"title":"Inverse Reinforcement Learning-Based Asynchronous Filtering for SMIB Power Systems With Stochastic Mode Switching","authors":"Weidi Cheng;Hai Wang;Yanyan Yin;Shuping He;Ho Ching Iu","doi":"10.1109/TCSI.2025.3627956","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3627956","url":null,"abstract":"This paper investigates the asynchronous filtering problem for single-machine infinite bus (SMIB) power systems subject to stochastic transmission line faults. The system is modeled as a discrete-time Markov jump system (MJS) to capture the random switching behavior induced by transmission line faults. To address the asynchrony between the system modes and the filter operation, a hidden Markov model (HMM) is adopted. The filtering problem is reformulated as a regulation problem by introducing a quadratic performance index based on output estimation errors, offering a filtering-based alternative to control strategies. To solve the associated coupled algebraic Riccati equations (CAREs), an inverse reinforcement learning (IRL)–based algorithm is developed, which enables model-free filtering without requiring prior knowledge of the system dynamics or transition probabilities. The convergence of the proposed algorithm is rigorously analyzed, and a numerical example based on an SMIB power system with stochastic faults is provided to validate its effectiveness.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2938-2951"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147571052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Framework of Digital Twin Based on State Space Model for Stability Assessment of 2-Stage 3-Phase Grid Connected PV System 基于状态空间模型的2级3相并网光伏系统稳定性评估数字孪生框架

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-10-23 DOI: 10.1109/TCSI.2025.3618651

Naresh Kumar Kumawat;Nishant Kumar

{"title":"Framework of Digital Twin Based on State Space Model for Stability Assessment of 2-Stage 3-Phase Grid Connected PV System","authors":"Naresh Kumar Kumawat;Nishant Kumar","doi":"10.1109/TCSI.2025.3618651","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3618651","url":null,"abstract":"The growing incorporation of power electronic converter-based renewable energy sources, such as solar Photovoltaic (PV) systems, has introduced a new challenge to grid stability due to the complex control dynamics and intermittent nature of sources. In this article, an innovative stability monitoring approach based on Digital Twin (DT) technology is presented for a two stage three phase grid connected photovoltaic system. A DT using concept of state space model is developed for a two stage three phase grid connected photovoltaic system based on mathematical model using Tustin transformation. A newly developed Discrete Damping ratio Adaptation Second Order Generalized Integrator-Frequency Locked Loop (DDASOGI-FLL) based Sliding Mode-Model Predictive Control (SM-MPC) and Adaptive Golden ratio based Electromagnetic Field Optimization (AG-EFO) algorithm are used for optimal performance of the entire system. Furthermore, the stability of the system and control are monitored periodically based on developed DT using the direct Lyapunov stability method. The stability assessments are conducted under various dynamic conditions such as unbalance & disturbance in grid voltage and irradiation change. To validate the accuracy of the developed DT and control strategies, a laboratory-based experimental prototype is developed.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"3013-3023"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147571038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variable Magnetic Permeability Coreless Transformers via Anti-Resonant Windings for Wide Input Voltage Range DC–DC Converters 宽输入电压范围DC-DC变换器用抗谐振绕组变磁导率无芯变压器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2026-04-01 Epub Date: 2025-08-14 DOI: 10.1109/TCSI.2025.3595564

Li Lai;Bo Zhang;Jingyang Lin;Lun Yang

{"title":"Variable Magnetic Permeability Coreless Transformers via Anti-Resonant Windings for Wide Input Voltage Range DC–DC Converters","authors":"Li Lai;Bo Zhang;Jingyang Lin;Lun Yang","doi":"10.1109/TCSI.2025.3595564","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3595564","url":null,"abstract":"To overcome the drawbacks of conventional coreless transformers (CLTs), where smaller magnetizing inductance results in large reactive power circulating current and switches’ turn-off current, this paper proposes a variable magnetic permeability CLT for wide input voltage range DC-DC converters via anti-resonant winding. Compared with the resonant converter using conventional two-winding CLT, the proposed converter exhibits lower switching loss and conduction loss on the primary side. These advantages come from the fact that the magnetic permeability and magnetizing impedance of CLTs can be greatly increased by adding the <italic>LC</i> anti-resonant winding. Besides, compared with the ferrite-core resonant converter, both have the same external characteristics, and crucially, the proposed converter has a lighter weight and smaller volume by multiplexing the leakage inductance into a resonant inductance, while ensuring ZVS and a wide input voltage range. A detailed analysis of the proposed converter, including the variable magnetic permeability, the voltage gain, and the wide voltage range modulation, is presented, and a design method is given. Finally, an experimental prototype with an input voltage range of 250-400V and 72V/1kW output is designed to verify the theoretical analysis.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 4","pages":"2975-2985"},"PeriodicalIF":5.2,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147571042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0