IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

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IEEE Circuits and Systems Society Information
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-02-26 DOI: 10.1109/TCSI.2025.3541500
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引用次数: 0
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-02-26 DOI: 10.1109/TCSI.2025.3541498
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引用次数: 0
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-02-26 DOI: 10.1109/TCSI.2025.3541496
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引用次数: 0
Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-30 DOI: 10.1109/TCSI.2025.3531008
Mohamed Nadeem;Chandan Kumar Jha;Rolf Drechsler
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引用次数: 0
IEEE Circuits and Systems Society Information
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3527913
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引用次数: 0
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3527909
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引用次数: 0
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3527911
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2025.3527911","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3527911","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"976-976"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857608","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies—AsianHOST 2023
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2024.3521308
Xinmiao Zhang;Chongyan Gu;Mengmei Ye;Qiang Liu;Reza Azarderakhsh;Weiqiang Liu;Yang Li
{"title":"Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies—AsianHOST 2023","authors":"Xinmiao Zhang;Chongyan Gu;Mengmei Ye;Qiang Liu;Reza Azarderakhsh;Weiqiang Liu;Yang Li","doi":"10.1109/TCSI.2024.3521308","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3521308","url":null,"abstract":"If no abstract provided do not include one in the JATS XML","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"482-482"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857680","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143184081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3525653
Zhengzhe Wei;Junjie Mu;Yuanjin Zheng;Tony Tae-Hyoung Kim;Bongjin Kim
{"title":"A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements","authors":"Zhengzhe Wei;Junjie Mu;Yuanjin Zheng;Tony Tae-Hyoung Kim;Bongjin Kim","doi":"10.1109/TCSI.2025.3525653","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3525653","url":null,"abstract":"This work proposes the Poisson equation formulation of the Retinex model for image enhancements using a low-power graph hardware accelerator performing finite difference updates on a lattice graph processing element (PE) array. By encapsulating the underlying algorithm in a graph hardware structure, a highly localized dataflow that takes advantage of the physical placement of the PEs is enabled to minimize data movement and maximize data reuse. The on-chip dataflow that achieves data sharing, and reuse among neighboring PEs during massively parallel updates is generated in each PE driven by two external control signals. Using a custom accumulator design intended for bit-serial computing, this work enables precision on demand and extensive on-chip data reuse with minimal area overhead, accommodating a non-overlap image mapping scheme in which a <inline-formula> <tex-math>$20times 20$ </tex-math></inline-formula> image tile can be processed without external memory access at a time. With increasing user-configurable update count, image noise and shadow can be progressively removed with the inevitable loss of image details. Fabricated using a 65nm technology, the test chip occupies 0.2955mm2 core area and consumes 2.191mW operating at 1V, 25.6MHz, and a reconfigurable 10- or 14-bit precision.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1346-1357"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-28 DOI: 10.1109/TCSI.2025.3528372
Shuai Wu;Yubing Li;Tao Tan;Zemeng Huang;Jiaze Qiao;Xiuping Li
{"title":"An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers","authors":"Shuai Wu;Yubing Li;Tao Tan;Zemeng Huang;Jiaze Qiao;Xiuping Li","doi":"10.1109/TCSI.2025.3528372","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3528372","url":null,"abstract":"This article presents an automated circuit topology generation and optimization method for RF low-noise amplifiers (LNAs). For circuit topology generation, a three-port small-signal model based on precomputed lookup tables (LUT) is proposed to accurately describe the transistors. Based on the model, a novel predefined building block (PBB) library for LNA is created and symbolically analyzed by three-port network parameters and noise correlation matrix. Then, graph-grammar-based tree structure generation (GTSG) is applied to efficiently realize circuit topology generation. For circuit optimization, the rule-guided non-dominated sorting genetic algorithm (RG-NSGA-II) is applied to optimize the performances of generated circuit topologies. To validate, four typical examples of X-band LNA based on a 130-nm CMOS process are presented, and the results are verified using Spectre. This method can automatically generate 936 size-free circuit topologies, even a variety of inspiring topologies. Compared to traditional NSGA-II, the RG-NSGA-II shows enhanced optimization speed in four examples, with the mean absolute percentage error (MAPE) <5% to Spectre.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1126-1139"},"PeriodicalIF":5.2,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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