Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency

Abstract

This paper presents a design-oriented analysis for the time-interleaved SAR ADC that quantifies different sources of imperfections to provide a unified design framework. This includes both single-channel and interleaving imperfections. A prototype time-interleaved ADC is designed and fabricated in a 28 nm CMOS process to validate the effectiveness of the theory. With one-time foreground timing skew and offset compensation, the 3.5 GS/s 11-bit time-interleaved SAR ADC achieves 55.6 dB SNDR at low input frequency and 54.3 dB SNDR at Nyquist frequency while dissipating 66.0 mW at 1 V supply including 14.8 mW clock buffer power.