IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Phase Modulated Bistatic Radar With an Analog Correlator: A Systematic Study","authors":"Wen Zhou;Yahya Tousi","doi":"10.1109/TCSI.2025.3529678","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3529678","url":null,"abstract":"This work presents a phase-modulated radar based on an analog correlator. We demonstrate a novel radar architecture that combines the energy efficiency of analog processing and the accuracy and flexibility of digital processing while avoiding their respective pitfalls. We introduce the proposed analog correlator, describe its theory of operation, and develop a numerical model to analyze and predict the output and the detection sensitivity. Next, we perform a thorough architectural analysis and present system-level simulations of the proposed structure. Finally, based on this investigation we derive circuit requirements and perform extensive radar simulations characterizing the performance of the implemented analog correlator. There is agreement between theoretical derivations, expected performance from system-level models, and the resulting performance from circuit-level time-domain simulations, demonstrating the feasibility of the proposed scheme for high-performance pulse-modulated radars.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1204-1217"},"PeriodicalIF":5.2,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler","authors":"Yoichi Iizuka;Akihide Maezono;Wataru Saito;Kazuhiko Takami;Fukashi Morishita","doi":"10.1109/TCSI.2025.3528426","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3528426","url":null,"abstract":"This document presents a CMOS image sensor (CIS) with a high-speed single slope ADC(SS-ADC) that has a novel high-speed counter and can reduce temporal noise in a wide range of frequency components by enabling correlated multiple sampling (CMS) and digital correlated double sampling (DCDS) at high frame rates. The test chip was fabricated in 55nm process and has 8.3M pixels. The counter was confirmed to operate at a frequency equivalent to 5.36GHz. It uses a circuit and dedicated counter code that suppresses differential non-linearity (DNL) deterioration due to faster counter speeds. When CMS is performed 4 times at 30 frames per second (fps), the random noise is 187uVrms, which is a 31% improvement in noise compared to when CMS is not performed.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1105-1113"},"PeriodicalIF":5.2,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece","authors":"Haochen Zhang;Xinyuan Qiao;Jing Tian;Suwen Song;Zhongfeng Wang","doi":"10.1109/TCSI.2025.3528119","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3528119","url":null,"abstract":"Classic McEliece, with a remarkably stable security level, has been selected as one of the four key-establishment algorithms in the fourth-round evaluation of the post-quantum cryptography (PQC) standardization process of national institute of standards and technology (NIST). However, its memory-intensive and time-consuming key generation poses an obstacle to widespread use. In this paper, we propose a fast hardware implementation of the key generation incorporating several architectural optimizations. For the Gaussian elimination, we optimize the scheduling of computing resources and the memory access process and present a high-performance and flexible systemizer with multiple low fan-out systolic arrays. Besides, an algorithmic-level parallelized design for entry generation and Gaussian elimination is proposed to reduce the redundant computation time. A compact entry generator with a multi-level feedback mechanism and a 2-D high-speed FFT module facilitates continuous streaming the generated entries into the systemizer.FPGA implementation results show that our designs for the key generation improve time-area efficiency by 11.9% to 43.2% compared to the state-of-the-arts. Moreover, compared to the hardware implementations for the key generation of the other two quasi-cyclic code-based PQC algorithms, ours for Classic McEliece based on the random code achieves close to or better results in several metrics.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1321-1331"},"PeriodicalIF":5.2,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Pixel Noise in Dynamic Vision Sensors","authors":"Donghwan Seo;Jung-Geun Kim;Injune Yeo;Hyunkeun Lee;Byung-Geun Lee","doi":"10.1109/TCSI.2025.3526965","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526965","url":null,"abstract":"To date, pixel noise in a dynamic vision sensor (DVS) has not been accurately analyzed in the literature, and its optimization has been performed empirically. This paper presents a theoretical analysis of the DVS pixel noise. The mean-squared noise voltage at the pixel output from each noise source in a pixel is mathematically derived and verified based on simulations and measurements. A design method to determine the pixel bias currents for a given photocurrent is also presented based on the noise analysis to improve noise performance while maintaining pixel latency. A prototype DVS chip was fabricated in a 110 nm complementary metal-oxide-semiconductor image sensor process and tested under various light and pixel bias conditions. It is shown that the proposed noise analysis and design method successfully predicted the noise performance of the DVS chip.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1081-1092"},"PeriodicalIF":5.2,"publicationDate":"2025-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Coding Unit Depth Identification Using Texture and Multiple Deep Learning Architectures","authors":"Hari Pattimi;Kota Naga Srinivasarao Batta;Polamarasetty Praveen Kumar;Ramakrishna S. S. Nuvvula;Baseem Khan;Aanchal Verma;R. K. Saket","doi":"10.1109/TCSI.2025.3526636","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526636","url":null,"abstract":"High-Efficiency Video Coding (HEVC), often known as H.265, is a new video coding standard that offers substantially better compression efficiency than the previous standard, H.264 while maintaining the same video quality. In HEVC, the quadtree partition method divides Coding Tree Units (CTUs) into Coding Units (CUs). This coding unit partition is recursive and increases computational complexity because it is dependent on rate-distortion optimization (RDO). In this paper, we propose a texture and deep learning-based system, that initiates the CU partition by the calculation of the CU texture attributes. Coding units are classified into three categories based on texturing properties. Class 1 represents mostly homogeneous regions, Class 2 mostly non-homogeneous regions, and Class 3 other regions. Only class 3 blocks are sent through the deep learning architecture. As a result, the total number of blocks partitioned by the deep learning architecture is lowered. We also proposed three distinct deep learning-based architectures in our system for coding unit partitioning, which eliminates the need for rate-distortion optimization and thereby decreases computational complexity. The input to our proposed texture and deep learning-based system is an image of size <inline-formula> <tex-math>$64times 64$ </tex-math></inline-formula> (CTU), while the output is a <inline-formula> <tex-math>$1times 16$ </tex-math></inline-formula> vector representing the depths of the coding tree unit. Simulation results demonstrate the effectiveness of our proposed system. Compared to existing models, our proposed CU-CNN, CU-MobileNet, and CU-Resnet have reduced the encoding time of CU partitions by 68.41%, 75.77%, and 88.08% respectively. In addition, the results demonstrated that the proposed system with the CU-MobileNet model is appropriate for mobile or lightweight applications, while the CU-Resnet model works well for time-critical or high-speed applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1372-1382"},"PeriodicalIF":5.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations","authors":"Léopold Van Brandt;Michele Bonnin;Mauricio Banaszeski da Silva;Pascal Bolcato;Gilson I. Wirth;Denis Flandre;Jean-Charles Delvenne","doi":"10.1109/TCSI.2024.3525387","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3525387","url":null,"abstract":"Stability of ultra-low-voltage SRAM bitcells in retention mode is threatened by two types of uncertainty: process variability and intrinsic noise. While variability dominates the failure probability, noise-induced bit flips in weakened bitcells lead to dynamic instability. We study both effects jointly in a unified SPICE simulation framework. Starting from a synthetic representation of process variations introduced in a previous work, we identify the cases of poor noise immunity that require thorough noise analyses. Relying on a rigorous and systematic methodology, we simulate them in the time domain so as to emulate a true data retention operation. Short times to failure, unacceptable for a practical ultra-low-power memory system application, are recorded. The transient bit-flip mechanism is analyzed and a dynamic failure criterion involving the unstable steady state is established. We conclude that, beyond static variability, the dynamic noise inflates defectiveness among SRAM bitcells. Then, a stochastic nonlinear model, fully characterizable from conventional deterministic SPICE simulations, is presented. We then leverage it to efficiently and accurately predict the mean time to failure with an analytical Eyring-Kramers formula, recently extended to account for the varying-noise behavior of nonlinear systems.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"989-1002"},"PeriodicalIF":5.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detection and Mitigation of nBTI Aging of a High Precision Current Comparator in 16 nm FinFET Technology","authors":"Hyuk Sun;Paul Wilkins;Steve Rose;Gil Engel","doi":"10.1109/TCSI.2025.3526099","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526099","url":null,"abstract":"Aging effects in deep sub-micron CMOS have become significant design challenges, particularly in precision analog circuits, not only due to the inaccuracy of aging modeling and simulators, but also a lack of detection methods incorporated into problematic silicon. In this work, we introduce a detection method to sense aging-related degradations in a precision current comparator, fabricated in 16nm FinFET technology. Utilizing this method we found that nBTI aging-related degradation results in a time-varying and memory-dependent hysteresis in the comparator. We propose two different mitigation methods: stress-balance and clamp diode attenuation schemes. The stress-balance mitigation scheme helps to balance any residual aging-related hysteresis on the comparator, whereas the clamp diode attenuation scheme reduces the aging-related degradation. Finally, the proposed aging-related mitigation schemes have been verified with silicon measurement data.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1017-1028"},"PeriodicalIF":5.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editorial A New Exciting Year Ahead for TCAS-I","authors":"José M. De La Rosa","doi":"10.1109/TCSI.2024.3507472","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3507472","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"1-1"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10835846","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3513753","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513753","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10835845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3513755","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513755","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"481-481"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10835840","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}