IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第2页

IEEE Circuits and Systems Society Information

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3527913

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IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3527909

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IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3527911

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Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies—AsianHOST 2023

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2024.3521308

Xinmiao Zhang;Chongyan Gu;Mengmei Ye;Qiang Liu;Reza Azarderakhsh;Weiqiang Liu;Yang Li

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A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3525653

Zhengzhe Wei;Junjie Mu;Yuanjin Zheng;Tony Tae-Hyoung Kim;Bongjin Kim

{"title":"A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements","authors":"Zhengzhe Wei;Junjie Mu;Yuanjin Zheng;Tony Tae-Hyoung Kim;Bongjin Kim","doi":"10.1109/TCSI.2025.3525653","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3525653","url":null,"abstract":"This work proposes the Poisson equation formulation of the Retinex model for image enhancements using a low-power graph hardware accelerator performing finite difference updates on a lattice graph processing element (PE) array. By encapsulating the underlying algorithm in a graph hardware structure, a highly localized dataflow that takes advantage of the physical placement of the PEs is enabled to minimize data movement and maximize data reuse. The on-chip dataflow that achieves data sharing, and reuse among neighboring PEs during massively parallel updates is generated in each PE driven by two external control signals. Using a custom accumulator design intended for bit-serial computing, this work enables precision on demand and extensive on-chip data reuse with minimal area overhead, accommodating a non-overlap image mapping scheme in which a <inline-formula> <tex-math>$20times 20$ </tex-math></inline-formula> image tile can be processed without external memory access at a time. With increasing user-configurable update count, image noise and shadow can be progressively removed with the inevitable loss of image details. Fabricated using a 65nm technology, the test chip occupies 0.2955mm2 core area and consumes 2.191mW operating at 1V, 25.6MHz, and a reconfigurable 10- or 14-bit precision.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1346-1357"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network of ECG Signal

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-29 DOI: 10.1109/TCSI.2025.3533544

Shin-Chi Lai;Szu-Ting Wang;S. M. Salahuddin Morsalin;Jia-He Lin;Shih-Chang Hsia;Chuan-Yu Chang;Ming-Hwa Sheu

{"title":"VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network of ECG Signal","authors":"Shin-Chi Lai;Szu-Ting Wang;S. M. Salahuddin Morsalin;Jia-He Lin;Shih-Chang Hsia;Chuan-Yu Chang;Ming-Hwa Sheu","doi":"10.1109/TCSI.2025.3533544","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3533544","url":null,"abstract":"The Electrocardiogram (ECG) test detects and records cardiac-related electrical activity of the heart. The ECG test identifies and documents cardiac-related electrical activity in the heart. The use of ECG signals for cardiovascular disease nursing as a crucial component of preoperative evaluation is increasing. ECG signals need to denoise and display in a clear waveform due to the numerous noises. We have introduced Compact Shortcut Denoising Auto-encoder (CS-DAE) neural network, which reduces the noise from ECG signals. The Compact Shortcut approach compresses the features passed through the shortcut layers, which lowers the operation’s memory needs and improves the noise reduction impact. In addition, the encoder and decoder process the Pixel-Unshuffled and Pixel-Shuffled, which effectively mitigates the feature loss caused by down-sampling and up-sampling operations. As a result, the CS-DAE algorithm decreases the computation and required memory size while maintaining higher accuracy. We have used MITDB and NSTDB datasets for training and testing the proposed CS-DAE model, resulting in the average Percentage of Root Mean Square Difference (PRD) being 46.30% and the improvement of Signal-to-Noise Ratio (SNRimp) being 10.50. In addition, we have designed VLSI architect ure for the proposed CS-DAE neural network to accelerate low hardware cost and less computation. The TUL PYNQTM-Z2 development platform runs the Verilog code, which is used for VLSI architecture and has the lowest power consumption of 1.65W.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1621-1633"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Adaptive Tracking Control of Constrained Nonlinear Systems and Its Application to Circuit Systems

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-28 DOI: 10.1109/TCSI.2025.3532481

Linghuan Kong;Shuang Zhang;Yifan Wu;Chen Sun;Wei He;Carlos Silvestre

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An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-28 DOI: 10.1109/TCSI.2025.3528372

Shuai Wu;Yubing Li;Tao Tan;Zemeng Huang;Jiaze Qiao;Xiuping Li

{"title":"An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers","authors":"Shuai Wu;Yubing Li;Tao Tan;Zemeng Huang;Jiaze Qiao;Xiuping Li","doi":"10.1109/TCSI.2025.3528372","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3528372","url":null,"abstract":"This article presents an automated circuit topology generation and optimization method for RF low-noise amplifiers (LNAs). For circuit topology generation, a three-port small-signal model based on precomputed lookup tables (LUT) is proposed to accurately describe the transistors. Based on the model, a novel predefined building block (PBB) library for LNA is created and symbolically analyzed by three-port network parameters and noise correlation matrix. Then, graph-grammar-based tree structure generation (GTSG) is applied to efficiently realize circuit topology generation. For circuit optimization, the rule-guided non-dominated sorting genetic algorithm (RG-NSGA-II) is applied to optimize the performances of generated circuit topologies. To validate, four typical examples of X-band LNA based on a 130-nm CMOS process are presented, and the results are verified using Spectre. This method can automatically generate 936 size-free circuit topologies, even a variety of inspiring topologies. Compared to traditional NSGA-II, the RG-NSGA-II shows enhanced optimization speed in four examples, with the mean absolute percentage error (MAPE) <5% to Spectre.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1126-1139"},"PeriodicalIF":5.2,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Phase Modulated Bistatic Radar With an Analog Correlator: A Systematic Study

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-27 DOI: 10.1109/TCSI.2025.3529678

Wen Zhou;Yahya Tousi

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Spiketrum: An FPGA-Based Implementation of a Neuromorphic Cochlea

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-01-27 DOI: 10.1109/TCSI.2025.3526585

Mhd Anas Alsakkal;Jayawan Wijekoon

{"title":"Spiketrum: An FPGA-Based Implementation of a Neuromorphic Cochlea","authors":"Mhd Anas Alsakkal;Jayawan Wijekoon","doi":"10.1109/TCSI.2025.3526585","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3526585","url":null,"abstract":"This paper presents a novel FPGA-based neuromorphic cochlea, leveraging the general-purpose spike-coding algorithm, Spiketrum. The focus of this study is on the development and characterization of this cochlea model, which excels in transforming audio vibrations into biologically realistic auditory spike trains. These spike trains are designed to withstand neural fluctuations and spike losses while accurately encapsulating the spatial and precise temporal characteristics of audio, along with the intensity of incoming vibrations. Noteworthy features include the ability to generate real-time spike trains with minimal information loss and the capacity to reconstruct original signals. This fine-tuning capability allows users to optimize spike rates, achieving an optimal balance between output quality and power consumption. Furthermore, the integration of a feedback system into Spiketrum enables selective amplification of specific features while attenuating others, facilitating adaptive power consumption based on application requirements. The hardware implementation supports both spike-based and non-spike-based processors, making it versatile for various computing systems. The cochlea’s ability to encode diverse sensory information, extending beyond sound waveforms, positions it as a promising sensory input for current and future spike-based intelligent computing systems, offering compact and real-time spike train generation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1648-1656"},"PeriodicalIF":5.2,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0