IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第2页

Fanout-Based Reliability Model for SER Estimation in Combinational Circuits 用于组合电路 SER 估计的基于扇出的可靠性模型

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3458864

Esfandiar Esmaieli, Yasser Sedaghat, Ali Peiravi

引用次数: 0

Structure-Varying Complex Network Chaotic Model and Its Hardware Implementation 结构变化复杂网络混沌模型及其硬件实现

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3455409

Chenyu Wang, Jun Zheng, Yining Qian

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Universal Finite-Time Observer-Based ITSMC for Converter-Driven Motor Systems With Disturbances 基于有限时间观测器的通用 ITSMC，适用于有干扰的变频器驱动电机系统

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3457838

Zhongding Zhang, Zeyu Guo, Zuo Wang, Shihua Li

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An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver 在 28-nm CMOS 有线接收器中使用减少分支最大似然序列检测的自适应 56-Gb/s Duo-PAM4 检测器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3453411

Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang

引用次数: 0

An Automated Fault Attack Framework for Block Ciphers Through Property Mining and Verification 通过属性挖掘和验证的块密码自动故障攻击框架

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-17 DOI: 10.1109/tcsi.2024.3456787

Xingxin Wang, Wei Hu, Shibo Tang, Xinxin Wang, Huisi Zhou

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Analysis and Design of Wideband Active Single-Sideband Time Modulator in 0.13-$mu$m CMOS 0.13-$mu$m CMOS 宽带有源单边带时间调制器的分析与设计

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-17 DOI: 10.1109/tcsi.2024.3456237

Guoxiao Cheng, Jin-Dong Zhang, Qiaoyu Chen, Wen Wu

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Offset Boosting-Oriented Construction of Multi-Scroll Attractor via a Memristor Model 通过忆阻器模型构建以偏移升压为导向的多辊吸引器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-16 DOI: 10.1109/tcsi.2024.3455350

Yongxin Li, Chunbiao Li, Sen Zhang, Yuanjin Zheng, Guanrong Chen

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LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory LLD：针对 3-D TLC NAND 闪存的 LDPC 硬解码轻量级延迟降低方案

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-16 DOI: 10.1109/TCSI.2024.3438789

Debao Wei;Yongchao Wang;Hua Feng;Huqi Xiang;Liyan Qiao

{"title":"LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory","authors":"Debao Wei;Yongchao Wang;Hua Feng;Huqi Xiang;Liyan Qiao","doi":"10.1109/TCSI.2024.3438789","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3438789","url":null,"abstract":"The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4611-4623"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142376906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 $mu$W at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier 采用双斜率时间放大器的 12 ps 精度两步时-数转换器，在 180 nm CMOS 上以 1 MS/s 的速度消耗 434 $mu$W

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-13 DOI: 10.1109/tcsi.2024.3454793

Xinchi Xu, Yonggang Wang, Yonghang Zhou, Zhengqi Song, Bo Wu, Xin Lin

引用次数: 0

A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination 用于视觉 SLAM 的 RANSAC 算法的实时和高精度硬件实现，实现错配特征点对消除

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-12 DOI: 10.1109/TCSI.2024.3422082

Wenzheng He;Zikuo Lu;Xin Liu;Ziwei Xu;Jingshuo Zhang;Chen Yang;Li Geng

{"title":"A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination","authors":"Wenzheng He;Zikuo Lu;Xin Liu;Ziwei Xu;Jingshuo Zhang;Chen Yang;Li Geng","doi":"10.1109/TCSI.2024.3422082","DOIUrl":"10.1109/TCSI.2024.3422082","url":null,"abstract":"The visual SLAM (vSLAM) algorithm is becoming a research hotspot in recent years because of its low cost and low delay. Due to the advantage of fitting irregular data input, random sample consensus (RANSAC) has become a commonly used method in vSLAM to eliminate mismatched feature point pairs in adjacent frames. However, the huge number of iterations and computational complexity of the algorithm make the hardware implementation and integration of the entire system challenging. This paper pioneeringly proposes an efficient hardware acceleration design with homography matrix as RANSAC hypothesis model, which achieves high speed and high precision. Through optimizing the direct linear transformation (DLT) method, the delay and resource consumption are reduced. The design is implemented on FPGA. Through the verification of Xilinx Zynq 7100 platform, the processing frame rate on EuRoc dataset is 709 fps, reaching an average speed up of \u0000<inline-formula> <tex-math>$263.2times $ </tex-math></inline-formula>\u0000 against ARM CPU, and a speed up of \u0000<inline-formula> <tex-math>$1.2sim 50.0times $ </tex-math></inline-formula>\u0000 compared with the advanced implementations in RANSAC part, which fully meets the real-time requirements. In addition, the root-mean-square error (RMSE) based on an open-source SLAM system (ICE-BA) on the EuRoc dataset reached 0.105 m, achieving an improvement of 15.6% in precision compared to the original ICE-BA system.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5102-5114"},"PeriodicalIF":5.2,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0