VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network of ECG Signal

Abstract

The Electrocardiogram (ECG) test detects and records cardiac-related electrical activity of the heart. The ECG test identifies and documents cardiac-related electrical activity in the heart. The use of ECG signals for cardiovascular disease nursing as a crucial component of preoperative evaluation is increasing. ECG signals need to denoise and display in a clear waveform due to the numerous noises. We have introduced Compact Shortcut Denoising Auto-encoder (CS-DAE) neural network, which reduces the noise from ECG signals. The Compact Shortcut approach compresses the features passed through the shortcut layers, which lowers the operation’s memory needs and improves the noise reduction impact. In addition, the encoder and decoder process the Pixel-Unshuffled and Pixel-Shuffled, which effectively mitigates the feature loss caused by down-sampling and up-sampling operations. As a result, the CS-DAE algorithm decreases the computation and required memory size while maintaining higher accuracy. We have used MITDB and NSTDB datasets for training and testing the proposed CS-DAE model, resulting in the average Percentage of Root Mean Square Difference (PRD) being 46.30% and the improvement of Signal-to-Noise Ratio (SNRimp) being 10.50. In addition, we have designed VLSI architect ure for the proposed CS-DAE neural network to accelerate low hardware cost and less computation. The TUL PYNQTM-Z2 development platform runs the Verilog code, which is used for VLSI architecture and has the lowest power consumption of 1.65W.