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IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

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Hybrid-Diode-Based Shinriki Circuit: Coexisting Oscillations and Bifurcation Trees 基于混合二极管的信利电路：共存振荡和分叉树
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-10 DOI: 10.1109/tcsi.2024.3453605
Fuhong Min, Sipeng Yin, Yizi Cheng
{"title":"Hybrid-Diode-Based Shinriki Circuit: Coexisting Oscillations and Bifurcation Trees","authors":"Fuhong Min, Sipeng Yin, Yizi Cheng","doi":"10.1109/tcsi.2024.3453605","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3453605","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive Event-Triggered Control for PDE-ODE Cascade Systems via Hierarchical Sliding Mode 通过分层滑动模式实现 PDE-ODE 级联系统的自适应事件触发控制
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-09 DOI: 10.1109/tcsi.2024.3446621
Shanlin Liu, Yingwei Zhang, Xudong Zhao
{"title":"Adaptive Event-Triggered Control for PDE-ODE Cascade Systems via Hierarchical Sliding Mode","authors":"Shanlin Liu, Yingwei Zhang, Xudong Zhao","doi":"10.1109/tcsi.2024.3446621","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3446621","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks 基于 NVM 的深度神经网络内存计算的特定 ADC
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-06 DOI: 10.1109/tcsi.2024.3430290
Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Haozhang Yang, Lifeng Liu, Linxiao Shen, Xiaoyan Liu, Jinfeng Kang, Peng Huang
{"title":"Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks","authors":"Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Haozhang Yang, Lifeng Liu, Linxiao Shen, Xiaoyan Liu, Jinfeng Kang, Peng Huang","doi":"10.1109/tcsi.2024.3430290","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3430290","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs :用于在低功耗 FPGA 上实时分析传感器数据的微型 RISC-V 控制 SNN 处理器
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-05 DOI: 10.1109/tcsi.2024.3450966
Gianluca Leone, Matteo Antonio Scrugli, Lorenzo Badas, Luca Martis, Luigi Raffo, Paolo Meloni
{"title":": A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs","authors":"Gianluca Leone, Matteo Antonio Scrugli, Lorenzo Badas, Luca Martis, Luigi Raffo, Paolo Meloni","doi":"10.1109/tcsi.2024.3450966","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3450966","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Q/V-Band CMOS Beamforming ICs and Integrated Phased-Array Antennas Q/V 波段 CMOS 波束成形集成电路和集成相控阵天线
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-05 DOI: 10.1109/tcsi.2024.3450668
Dixian Zhao, Weihan Gao, Ke Li, Hengzhi Wan, Qin Tian, Yongran Yi, Jiajun Zhang, Huiqi Liu
{"title":"Q/V-Band CMOS Beamforming ICs and Integrated Phased-Array Antennas","authors":"Dixian Zhao, Weihan Gao, Ke Li, Hengzhi Wan, Qin Tian, Yongran Yi, Jiajun Zhang, Huiqi Liu","doi":"10.1109/tcsi.2024.3450668","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3450668","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lipschitz Stability Estimate for an Initial Wave Reconstruction Problem of Telegraph Type With Gaussian Noise 有高斯噪声的电报型初始波重建问题的 Lipschitz 稳定性估计
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3451505
Dat-Thuc Nguyen, Ngoc Tuan Duong, Vo Anh Khoa
{"title":"Lipschitz Stability Estimate for an Initial Wave Reconstruction Problem of Telegraph Type With Gaussian Noise","authors":"Dat-Thuc Nguyen, Ngoc Tuan Duong, Vo Anh Khoa","doi":"10.1109/tcsi.2024.3451505","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3451505","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ImSTDP: Implicit Timing On-Chip STDP Learning ImSTDP：隐式定时片上 STDP 学习
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3450958
Dedong Zhao, Oliver Schrape, Zoran Stamenkovic, Milos Krstic
{"title":"ImSTDP: Implicit Timing On-Chip STDP Learning","authors":"Dedong Zhao, Oliver Schrape, Zoran Stamenkovic, Milos Krstic","doi":"10.1109/tcsi.2024.3450958","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3450958","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS 采用 90 纳米 SiGe BiCMOS 设计 64-GBaud 相干互阻抗放大器的信号完整性增强技术
IF 5.2 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/TCSI.2024.3450700
Shuaizhe Ma;Nianquan Ran;Xi Liu;Yifei Xia;Songqin Xu;Wei Huang;Chen Tan;Jing Li;Zhenyu Yin;Shaoheng Lin;Jianhua Pan;Zhe Chen;Chaoxuan Zhang;Wu Wen;Quan Pan;Zhongming Xue;Xiaoyan Gui;Li Geng;Dan Li
{"title":"Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS","authors":"Shuaizhe Ma;Nianquan Ran;Xi Liu;Yifei Xia;Songqin Xu;Wei Huang;Chen Tan;Jing Li;Zhenyu Yin;Shaoheng Lin;Jianhua Pan;Zhe Chen;Chaoxuan Zhang;Wu Wen;Quan Pan;Zhongming Xue;Xiaoyan Gui;Li Geng;Dan Li","doi":"10.1109/TCSI.2024.3450700","DOIUrl":"10.1109/TCSI.2024.3450700","url":null,"abstract":"This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between \u0000<inline-formula> <tex-math>$150~Omega $ </tex-math></inline-formula>\u0000 - 5 K\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces 一种单端 PAM-4 发射器，使用无堆叠无台阶 CML 驱动器和用于存储器接口的系数校正 FFE
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3450875
Yong-Un Jeong, Joo-Hyung Chae
{"title":"A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces","authors":"Yong-Un Jeong, Joo-Hyung Chae","doi":"10.1109/tcsi.2024.3450875","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3450875","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Throughput LDPC Decoder for Multiple Wireless Standards 适用于多种无线标准的高吞吐量 LDPC 解码器
IF 5.1 1区 工程技术
IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3419425
Wei Chen, Yajie Li, Dake Liu
{"title":"High-Throughput LDPC Decoder for Multiple Wireless Standards","authors":"Wei Chen, Yajie Li, Dake Liu","doi":"10.1109/tcsi.2024.3419425","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3419425","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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