IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3513757","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513757","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10836124","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 36.8-μW 66 nV/√Hz 85.7 dB-System-SNDR Reconfigurable Single-Channel ExG Acquisition System for Bio-Sensor Modules","authors":"Yuke Shen;Jiacheng Liu;Kui Wen;Yanbo Zhang;Yi Shen;Shubin Liu;Zhangming Zhu","doi":"10.1109/TCSI.2024.3523502","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3523502","url":null,"abstract":"This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula><inline-formula> <tex-math>$Sigma $ </tex-math></inline-formula>) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC) <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula><inline-formula> <tex-math>$Sigma $ </tex-math></inline-formula> modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula><inline-formula> <tex-math>$text {V}_{text {rms}}$ </tex-math></inline-formula> (0.5-100 Hz) and 1.93 to 3.51 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula><inline-formula> <tex-math>$text {V}_{text {rms}}$ </tex-math></inline-formula> (0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-<inline-formula> <tex-math>$text {V}_{text {pp}}$ </tex-math></inline-formula> differential input and can support 16<inline-formula> <tex-math>$times $ </tex-math></inline-formula> power/BW reconfigurability with ENOB>15 bit. The complete system occupies an active area of 0.56 mm2 and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1068-1080"},"PeriodicalIF":5.2,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Unified Accelerator for All-in-One Image Restoration Based on Prompt Degradation Learning","authors":"Siyu Zhang;Qiwei Dong;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TCSI.2024.3519532","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519532","url":null,"abstract":"All-in-one image restoration (IR) recovers images from various unknown distortions by a single model, such as rain, haze, and blur. Transformer-based IR methods have significantly improved the visual effects of the restored images. However, deploying complex IR models on edge devices is challenging due to massive parameters and intensive computations. Moreover, existing accelerators are typically customized for a single task, resulting in severe resource underutilization when executing multiple tasks. Therefore, this paper develops an algorithm-hardware co-design framework to accelerate a novel CNN-Transformer cooperative model for multiple IR tasks. Firstly, on the algorithm level, an Efficient Restoration Foundational Model (ERFM) is proposed to recover corrupted images from various degradations with low model complexity. Secondly, to guide adaptive corruption removal, a novel prompt learning scheme is introduced to fuse context-related degradation cues and boost high-quality reconstruction. Thirdly, on the hardware level, an integer approximation method is proposed to avoid expensive hardware overhead caused by complex nonlinear operations, such as layer normalization and softmax while maintaining comparable IR quality. Moreover, a head stationary dataflow and softmax fusion mechanism are designed to reduce data movement and enhance on-chip resource utilization. Finally, an overall hardware architecture is developed and implemented in TSMC 28 nm CMOS technology. Experimental results show that our ERFM achieves better visual perception than other baselines on seven challenging IR tasks without task-specific fine-tuning. Moreover, compared to other accelerators for vision Transformers, our design can achieve <inline-formula> <tex-math>$3.3times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$3.7times $ </tex-math></inline-formula> improvements in throughput and energy efficiency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1282-1295"},"PeriodicalIF":5.2,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2024 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 71","authors":"","doi":"10.1109/TCSI.2024.3521726","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3521726","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"1-112"},"PeriodicalIF":5.2,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10817113","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Wide Air Gap IPT System for Distribution Insulator Applications Based on Reconfigurable Autotransformer Coupling Structure","authors":"Peng Gu;Yunrui Hao;Xingzhen Guo;Dongsheng Yang;Peng Zhao;Bowen Zhou;Yijie Wang","doi":"10.1109/TCSI.2024.3519728","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519728","url":null,"abstract":"In this paper, an inductive power transfer (IPT) system for distribution insulator based on reconfigurable autotransformer magnetic coupler (ATMC) is proposed. A three-stage IPT system architecture is proposed based on the form of a 35kV insulator structure. A novel multi-tap magnetic coupler in the form of autotransformer is proposed. The voltage conversion ratio and output characteristics of the IPT system can be reconstructed by changing the winding taps connected to the IPT system. An ATMC-based IPT system circuit model is established. The parameters of ATMC are optimized. The effect of system parameter reconstruction by changing the winding taps of ATMC is analyzed. An IPT system based on a reconfigurable ATMC with three winding taps on both the primary and secondary sides is designed, an experimental prototype is built. <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> sets of experiments are completed, and the solution to reconstruct the system state by changing the winding taps of ATMC is verified. The maximum efficiency of the system is close to 90%.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"963-975"},"PeriodicalIF":5.2,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tsetlin Machine-Based Image Classification FPGA Accelerator With On-Device Training","authors":"Svein Anders Tunheim;Lei Jiao;Rishad Shafik;Alex Yakovlev;Ole-Christoffer Granmo","doi":"10.1109/TCSI.2024.3519191","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3519191","url":null,"abstract":"The Tsetlin Machine (TM) is a novel machine learning algorithm that uses Tsetlin automata (TAs) to define propositional logic expressions (clauses) for classification. This paper describes a field-programmable gate array (FPGA) accelerator for image classification based on the Convolutional Coalesced Tsetlin Machine. The accelerator classifies booleanized images of <inline-formula> <tex-math>$28times 28$ </tex-math></inline-formula> pixels into 10 classes, and is configured with 128 clauses in a highly parallel architecture. To achieve fast clause evaluation and class prediction, the TA action signals and the clause weights per class are available from registers. Full on-device training is included, and the TAs are implemented with 34 Block RAM (BRAM) instances which operate in parallel. Each BRAM is addressed by the clause number and has a 72-bit word width that supports 8 TAs. The design is implemented in a Xilinx Zynq Ultrascale+ XCZU7 FPGA. Running at 50 MHz, the accelerator core achieves 134k image classifications per second, with an energy consumption per classification of <inline-formula> <tex-math>$13.3~mu $ </tex-math></inline-formula> J. A single training epoch of 60k samples requires a processing time of 1.5 seconds. The accelerator obtains a test accuracy of 97.6% on MNIST, 84.1% on Fashion-MNIST and 82.8% on Kuzushiji-MNIST.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"830-843"},"PeriodicalIF":5.2,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors","authors":"Pradeep Kumar Gopalakrishnan;Chip-Hong Chang;Arindam Basu","doi":"10.1109/TCSI.2024.3517133","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3517133","url":null,"abstract":"The Dynamic Vision Sensor (DVS) is a bio-inspired image sensor which has many advantages such as high dynamic range, high bandwidth, high temporal resolution and low power consumption for Internet of Video Things and Edge Computing applications. However, spuriously generated Background Activity (BA) noise events can significantly degrade the quality of DVS output and cause unnecessary computations throughout the image processing chain, reducing its energy efficiency. Near-sensor filters can mitigate this problem by preventing the BA noise events from reaching downstream stages. In this paper, we propose a novel, hardware-efficient, spatio-temporal correlation filter (HAST) for near-sensor BA noise filtering. It uses compact two-dimensional binary arrays along with simple, arithmetic-free hash-based functions for storage and retrieval operations. This approach eliminates the need to use timestamps for determining the chronological order of events. HAST uses much lower memory and energy compared to other hardware-friendly filters (BAF/STCF) while matching their performance in simulations with standard datasets; for a sensor of resolution <inline-formula> <tex-math>$346times 260$ </tex-math></inline-formula> pixels, it requires only 5–18% of their memory, and about 15% of their energy per event for correlation time <inline-formula> <tex-math>$tau $ </tex-math></inline-formula> ranging from 1 to 50 ms. The memory and energy gains of the filter increase with sensor resolution. In FPGA implementation, HAST achieves about 29% higher throughput than BAF/STCF while utilizing only about 5% of their memory. The filter parameter values can be chosen by Design Space Exploration (DSE) for optimized performance-resource trade-offs based on application requirements.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1332-1345"},"PeriodicalIF":5.2,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 40 nm Cryo-CMOS Homodyne-Demodulation Readout SoC for Superconducting Qubits","authors":"Donggyu Minn;Kiseo Kang;Jaeho Lee;Seongchan Bae;Byungjun Kim;Jaehoon Lee;Jae-Yoon Sim","doi":"10.1109/TCSI.2024.3518472","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3518472","url":null,"abstract":"This paper presents a cryo-CMOS readout SoC based on a homodyne demodulation architecture with an integrating receiver. The homodyne receiver module for each qubit employs a dedicated local LO generator for a coherent detection under a frequency-division multiplexed multi-qubit readout environment. To mitigate the conventional issues of the homodyne demodulation in wireless communications, such as 1/f noise and DC offset by LO leakage, the proposed receiver incorporates effective calibration schemes by utilizing the specific operating conditions of the superconducting qubits. The implemented chip in 40 nm CMOS is tested at 4 K in a dilution refrigerator under an emulated SNR environment of superconducting qubit readout, i.e. -70 dBm input with a noise floor of -148 dBm/Hz. Measurement shows that circuit-only fidelity reaches 99% in 200 ns with an ideal single tone RF input. A back-to-back test using an on-chip 4-tone transmitter shows a 93 % circuit-only fidelity with 400 ns integration.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1003-1016"},"PeriodicalIF":5.2,"publicationDate":"2024-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memristor-Based Parallel Computing Circuit Optimization for LSTM Network Fault Diagnosis","authors":"Junwei Sun;Yuhan Cao;Yi Yue;Shiping Wen;Yanfeng Wang","doi":"10.1109/TCSI.2024.3516325","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3516325","url":null,"abstract":"Researchers often focus on algorithmic enhancements while overlooking the potential benefits of hardware improvements. In this paper, a memristor-based parallel computing circuit optimization for LSTM network fault diagnosis is proposed. In response to the slow convergence of the algorithm, the characteristics of the memristor can matrix the algorithm and import it into the hardware circuit. The amnesia parallelization strategy executes four iterative processes simultaneously. The convergence speed is improved. Using the high-speed capability of the amnesia in parallel matrix operations using memristive circuits, four circuit modules are designed:mutation, crossover, evolution, and selection. These modules are integrated into a memristor circuit network model. To efficiently complete the iterative process and make effective use of the memristor’s strong storage property, the best-fit values are stored. To validate the effectiveness of the algorithm, simulations and comparative experiments are conducted on the Case Western Reserve University (CWRU) dataset. The results show that the model optimised with memristor hardware circuitry has improved the accuracy by 98% and has better fault diagnosis performance. This research not only advances the integration of memristive devices in neural network optimization, showcasing significant implications for the design of advanced circuit systems in the era of intelligent computing.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"907-917"},"PeriodicalIF":5.2,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inverse Proportional Chaotification Model for Image Encryption in IoT Scenarios","authors":"Wenhao Liu;Kehui Sun;Huihai Wang;Binglun Li;Yongjiu Chen","doi":"10.1109/TCSI.2024.3511675","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3511675","url":null,"abstract":"In Internet of Things (IoT) scenarios, the limited computing resources and energy constraints of devices, alongside the growing demand for real-time applications, make secure image transmission challenging. To address this issue, we propose a lightweight image encryption scheme based on chaotic map. Firstly, a new 3-D inverse proportional chaotic map (3D-IPCM) is designed with good robustness. Dynamics confirms that it possesses key characteristics, including a broad and continuous chaotic range, all positive Lyapunov exponents (LEs), high permutation entropy (PE) complexity and even distribution. Then, a new pseudorandom number generator (PRNG) is designed based on this map, which successfully passes all NIST and TestU01 tests, even with 16-bit calculation precision. Next, this PRNG is employed for image encryption in IoT scenarios. In the cryptosystem, a chromosome crossover (CC)-based scrambling algorithm is proposed, along with a diffusion algorithm that achieves strong resistance to differential attack in just two rounds of row diffusion. Simulation and analysis verify that the cryptosystem has strong resistance to common attacks and low cost. For \u0000<inline-formula> <tex-math>$256 times 256$ </tex-math></inline-formula>\u0000 images, its average number of pixels change rate (NPCR) and unified average changing intensity (UACI) are 100% and 33.40%, respectively, and the encryption time is only 7.4 ms. Ultimately, we implement the algorithm on FPGA, thus confirming its capacity for parallel acceleration.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"254-264"},"PeriodicalIF":5.2,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}