IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"A Unified Sampled-Data Small-Signal Model for a Ripple-Based COT Buck Converter With Arbitrary Ripple Injection Network","authors":"Francesco Gabriele;Antonio Carlucci;Davide Lena;Fabio Pareschi;Riccardo Rovatti;Stefano Grivet-Talocia;Gianluca Setti","doi":"10.1109/TCSI.2025.3557278","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557278","url":null,"abstract":"In this paper, we present a novel and unified small-signal modeling technique for Pulse-Width Modulated (PWM) DC-DC Buck converters with Ripple-Based Constant On-Time (RBCOT) control. In fact, despite the spread of RBCOT-based converters in several applications requiring tight dynamic performances and a low architectural complexity, their description through small-signal models is not always as reliable as that of fixed-frequency PWM control architectures, and a general and exact modeling framework is not well established. The proposed methodology is grounded on the DC-DC converter state-space representation and thus, differently from other modeling techniques, it permits to fully characterize the dynamic behavior of generic RBCOT converter topologies with arbitrary complex power stage and ripple injection networks. As a case study, we derive the small-signal model for a Buck converter embedding a widely used ripple injection network in industrial applications. The validity of the theoretical results is confirmed through direct comparison with SIMetrix/SIMPLIS simulations and experimental measurements in practical application scenarios, confirming the accuracy of the model even well beyond the converter switching frequency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2942-2955"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rational-Exponent Filters with Applications to Generalized Exponent Filters","authors":"Samiya A. Alkhairy","doi":"10.1109/TCSI.2025.3545459","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3545459","url":null,"abstract":"We present filters with rational exponents in order to provide a continuum of filter behavior not classically achievable. We discuss their stability, the flexibility they afford, and various representations useful for analysis, design and implementations. We do this for a generalization of second-order filters which we refer to as rational-exponent Generalized Exponent Filters (GEFs) that are useful for a diverse array of applications. We present equivalent representations for rational-exponent GEFs in the time and frequency domains: transfer functions, impulse responses, and integral expressions - the last of which allows for efficient real-time processing without preprocessing requirements. Rational-exponent filters enable filter characteristics to be on a continuum rather than limiting them to discrete values thereby resulting in greater flexibility in the behavior of these filters without additional complexity in causality and stability analyses compared with classical filters. In the case of GEFs, this allows for having arbitrary continuous rather than discrete values for filter characteristics such as 1) the ratio of 3dB quality factor to maximum group delay - particularly important for filterbanks which have simultaneous requirements on frequency selectivity and synchronization; and 2) the ratio of 3dB to 15dB quality factors that dictates the shape of the frequency response magnitude.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2139-2152"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Generalized Discrete-Time Variable Gain ADRC for Nonlinear Systems and Its Application to Parallel Teleoperated Manipulators","authors":"Shaomeng Gu;Jinhui Zhang;Long Cheng;Yuanqing Wu","doi":"10.1109/TCSI.2025.3555204","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555204","url":null,"abstract":"In this paper, we propose a novel generalized discrete-time variable gain active disturbance rejection control (DTVGADRC) method for the <italic>n</i>-th order discrete-time nonlinear systems. The error-driven generalized DTVGADRC can dynamically improve the control performances, including generalized discrete-time variable gain tracking differentiator (DTVGTD), generalized discrete-time variable gain extended state observer (DTVGESO), and generalized discrete-time variable gain controller (DTVGC). Furthermore, the stability analysis of generalized DTVGADRC is performed, and the parameters in the variable gain functions are determined by the theoretical analysis. Finally, the generalized DTVGADRC method is applied to parallel teleoperated manipulators, and the experiment results are presented to illustrate effectiveness of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2868-2877"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Beam-Steering dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128 × 80 SPAD Sensor, and ML-Based Edge-Computing Object Detection","authors":"Yifan Wu;Miao Sun;Sifan Zhou;Tao Xia;Lei Wang;Jier Wang;Yuan Li;Ming Zhong;Rui Bai;Xuefeng Chen;Yuanjin Zheng;Patrick Yin Chiang;Shenglong Zhuo;Lei Qiu","doi":"10.1109/TCSI.2025.3550450","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550450","url":null,"abstract":"In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a <inline-formula> <tex-math>$128times 80$ </tex-math></inline-formula> resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a <inline-formula> <tex-math>$128times 80$ </tex-math></inline-formula> SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2089-2102"},"PeriodicalIF":5.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices","authors":"Hoai Luan Pham;Thi Diem Tran;Vu Trung Duong Le;Yasuhiko Nakashima","doi":"10.1109/TCSI.2025.3553837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553837","url":null,"abstract":"Classification is a crucial aspect of cardiovascular-related challenges, requiring thorough research and optimization to develop effective solutions for both patients and doctors. Recently, rapid advancements in artificial intelligence, particularly Convolutional Neural Networks (CNNs), have introduced numerous effective methods, significantly improving disease classification in Electrocardiogram (ECG) analysis. However, existing CNN-based accelerators often encounter challenges such as high parameter counts, limited flexibility in handling diverse CNN configurations, and inefficient hardware utilization. To address these issues, this paper proposes the Mini InceptionNet Accelerator (MINA), a hardware-efficient and flexible accelerator designed specifically for one-dimensional (1-D) CNN-based ECG classification. First, a novel 1-D CNN model, Mini InceptionNet, reduces the parameter count by 41.6% compared to the smallest existing 1-D CNN, minimizing memory requirements while maintaining high classification accuracy. Second, a flexible Processing Element Array (PEA) is designed with a Sharing Buffer Allocator (SBA) to support dynamic data coordination across various network topology parameters. Third, each Processing Element (PE) is equipped with four Local Data Memories (LDMs) and an ALU, enabling efficient intermediate data storage and versatile operations for modern CNN models. To demonstrate its effectiveness, MINA has been successfully implemented and verified on the ZCU102 FPGA at the system-on-chip level. FPGA evaluations show that MINA achieves <inline-formula> <tex-math>$1.3times - 2.9times $ </tex-math></inline-formula> higher energy efficiency (<italic>GOP/s/MeLUT</i>) than state-of-the-art 2-D CNN accelerators. Compared to existing 1-D CNN accelerators, MINA achieves at least <inline-formula> <tex-math>$1.53times $ </tex-math></inline-formula> improvement in the area-delay product (ADP). Additionally, weight pruning is discussed as a supporting strategy, achieving up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> faster inference time and a <inline-formula> <tex-math>$2.13times $ </tex-math></inline-formula> improvement in ADP at 70% sparsity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2740-2753"},"PeriodicalIF":5.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Application of Brain-Inspired Circuit With Context-Dependent and State-Dependent Memory","authors":"Gang Dou;Daoguo Li;Mei Guo;Herbert Ho-Ching Iu","doi":"10.1109/TCSI.2025.3554171","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554171","url":null,"abstract":"The context and the state of mind are important retrieval cues for long-term memory, which helps information to be retrieved quickly. However, most memristive circuits focus on the process of information memory, few studies consider the process of information retrieval. In this work, a brain-inspired circuit with context-dependent and state-dependent memory is proposed based on the three-level processing model of memory information, which integrates the processes of information memory and information retrieval. The circuit includes sensory memory module, short-term memory module, long-term memory module, information retrieval module, status module, and context module. In the circuit, information, contexts, and states are eventually transferred to long-term memory module for storage and retrieval. Meanwhile, the factors influencing information retrieval are considered, such as the degree of information memory, the time interval between information memory and retrieval, the context, and the state. And the proposed circuit has scalability, which realizes the memory of information in multiple contexts. Finally, based on the characteristics of memristors, the proposed circuit is extended for detecting damage to the machining accuracy of the mobile CNC lathe. Combining brain-inspired circuits with human memory mechanism, this work provides further reference for the research of brain-like intelligence.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2566-2577"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System","authors":"Sayan Sarkar;Yuan Yao;Wing-Hung Ki;Chi-Ying Tsui","doi":"10.1109/TCSI.2025.3550479","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3550479","url":null,"abstract":"A 13.56-MHz wireless power transfer (WPT) system with fully integrated transmitter (<inline-formula> <tex-math>${mathrm {T}}_{mathrm {X}}$ </tex-math></inline-formula>) and receiver (<inline-formula> <tex-math>${mathrm {R}}_{mathrm {X}}$ </tex-math></inline-formula>) chips is presented. The receiver’s output voltage is locally regulated using a linear current-sink-based regulator, while global power regulation is achieved at the transmitter through a hybrid control strategy that combines constant off-time and hysteretic control for a reconfigurable power amplifier. Synchronized load-shift keying at the receiver improves the relative change in the primary current of the transmitter by >15%. The adaptive digitally controlled active rectifier achieves a voltage conversion ratio (VCR) and power conversion efficiency (PCE) of 0.92 and 92.4%, respectively, for a <inline-formula> <tex-math>$200~Omega $ </tex-math></inline-formula> load resistance. The end-to-end efficiency is improved by 25% at heavy load and 14% at light load by enabling TX global power regulation. Both TX and RX chips were fabricated in the BCDlite 180 nm process with 1.8 V/5 V devices. This system achieves a greater operating distance, higher output power, and faster load-transient response while significantly reducing circuit and system design complexity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2061-2074"},"PeriodicalIF":5.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Super-Regenerative Reception Technique Based on an Improved General Theory in Linear Mode","authors":"Junhong Liu;Guangyin Feng;Yi Wu;Fanyi Meng;Xiuyin Zhang","doi":"10.1109/TCSI.2025.3552824","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3552824","url":null,"abstract":"Super-regenerative receivers (SRRs) hold great promise as a low-cost solution for wireless communication due to their low power and relative simplicity. However, previous researches have primarily concentrated on super-regenerative amplifiers/oscillators, leading to limited insights into SRRs with inappropriate assumptions or dispensable operations, such as synchronous quench and baseband oversampling. This paper presents an improved general theory of super-regenerative reception in the linear mode that provides more design insights for digital communication. By analyzing the time-domain model of a general super-regenerative circuit, we derived a comprehensive frequency-domain model based on a convolution method, through which a concept of signal-lobe transfer function is introduced. Based on the proposed model, the effects of quench jitter and residual phenomenon are analyzed. Furthermore, an asynchronous quench method is introduced, which eliminates the requirement of synchronization between the modulated symbol and the quench signal, thus reducing the system complexity. To eliminate the baseband oversampling, especially for high-speed communications, main-lobe filtering and sub-sampling techniques are also proposed. To verify this general theory and proposed techniques, two SRRs with main-lobe filtering and sub-sampling were designed with ideal components and simulated using Cadence Virtuoso. The simulation results of two SRRs match with the proposed model very well. Overall, this paper provides a comprehensive analysis of super-regenerative reception for digital communication and offers valuable insights into its potentials and limitations.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2578-2591"},"PeriodicalIF":5.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact 321–343-GHz Integrated CMOS Radiator by Co-Designing Ring Oscillator and Multifunctional Antenna","authors":"Jiawei Yang;Yizhu Shen;Zhenghuan Wei;Sanming Hu","doi":"10.1109/TCSI.2025.3554680","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554680","url":null,"abstract":"This work presents a compact integrated CMOS radiator with a tuning range of 321-343 GHz. The miniaturization and enhanced performance of the radiator is achieved through co-designing a ring oscillator and a multifunctional antenna. The multi-stage ring oscillator features a variable common-source (CS) stage, which is proposed to achieve a broad frequency tuning range. To enhance the performance of the proposed variable CS stage for terahertz (THz) oscillator, wideband load impedances for all harmonics are theoretically analyzed and recursively optimized. The multifunctional antenna integrates six key functions into a simple compact structure: 1) inherently embedding the ring oscillator within a symmetric layout to ensure uniform operation, 2) directly combining the desired third harmonic signals without bulky and lossy passive networks, 3) radiating the desired third harmonic, 4) suppressing unwanted even harmonics, 5) providing fundamental inductance for the ring oscillator, and 6) supplying DC bias at virtual ground. For experimental validation, a THz radiator including a four-stage ring oscillator and a multifunctional antenna, is co-designed and fabricated in 40 nm CMOS process. The total chip area is as compact as 0.12 mm<inline-formula> <tex-math>${}^{mathbf {2}}$ </tex-math></inline-formula>. The measured output power and EIRP are −3.6 dBm and −9 dBm at 343 GHz, respectively, with a low DC power consumption of 46 mW. Moreover, the CMOS THz radiator is with a measured frequency tuning range of 6.7%, and DC-to-<inline-formula> <tex-math>$P_{mathbf {out}}$ </tex-math></inline-formula> efficiency of 0.95%. This compact radiator demonstrates promising potential for wideband and high-efficiency THz applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2603-2613"},"PeriodicalIF":5.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bursting Oscillations Induced by the Variable Discontinuous Boundary in Chua’s Circuit","authors":"Wenjie Zuo;Yi Zhang;Jin Song;Yuxun Zhu;Zhengdi Zhang","doi":"10.1109/TCSI.2025.3553484","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553484","url":null,"abstract":"Bursting oscillations and bifurcation mechanisms in piecewise circuit systems have long been a research focus in the fields of dynamics and control. While most previous studies have focused on systems with a fixed discontinuous boundary, this paper examines systems with a variable discontinuous boundary. We develop a mathematical model based on Chua’s circuit and present numerical simulations of bursting oscillations under varying parameters. The impact of the translation of the discontinuous boundary (TDB) on the system’s topological structure and non-smooth bifurcations is analyzed. By combining the two-parameter bifurcation set of equilibrium points with the superposition diagram of the transformed phase diagram (TPD), we reveal mechanisms behind different bursting modes induced by the TDB. A Multisim-based simulation circuit is designed to validate the research results. It is found that the topology of the equilibrium branches of each subsystem remains the same during the TDB, but the number of smooth bifurcations changes due to the switching between subsystems. The TDB also alters the characteristics of the boundary equilibrium point, leading to the catastrophic disappearance or emergence of non-smooth limit cycles, which consequently changes the number of spiking oscillations. Moreover, the interaction of the slow passage effect (SPE) and the TDB causes the trajectory to remain in a delayed segment, affecting the number of spiking oscillations per period. Additionally, the TDB may lead to the disappearance of bursting oscillations, then the system exhibits a behavior similar to that of simple harmonic motion. Our study expands the scope of research on piecewise-smooth circuit systems.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2768-2777"},"PeriodicalIF":5.2,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}