IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第3页

Design and Implementation of a Low-Complexity Continuously Variable Digital Filter Using a Novel Farrow-Equivalent-Newton Structure-Based Fractional Delay Filter 基于新型Farrow-Equivalent-Newton结构的分数阶延迟滤波器的低复杂度连续可变数字滤波器的设计与实现

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-23 DOI: 10.1109/TCSI.2025.3560980

T. C. Jayasree;J. C. Suneina;T. Bindima;M. P. Gilesh

{"title":"Design and Implementation of a Low-Complexity Continuously Variable Digital Filter Using a Novel Farrow-Equivalent-Newton Structure-Based Fractional Delay Filter","authors":"T. C. Jayasree;J. C. Suneina;T. Bindima;M. P. Gilesh","doi":"10.1109/TCSI.2025.3560980","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560980","url":null,"abstract":"Variable filters with adjustable bandwidth are vital components in diverse communication scenarios. This paper presents an innovative architecture for a continuously variable bandwidth filter using a fixed hardware. Our approach integrates a fixed finite impulse response filter between two arbitrary fractional delay filters implemented through a novel Farrow-equivalent-Newton structure. The proposed architecture provides a low-complexity implementation structure compared to the state-of-the-art approaches. A precise mapping equation for the edge frequencies of the filters generated from the proposed continuously variable bandwidth filter, in terms of a variable parameter called the resampling ratio, is also formulated. Validation experiments encompass the design of continuously variable bandwidth filters tailored to various wireless communication standards. The hardware utilization report of the proposed continuously variable bandwidth filter obtained by synthesizing the structure using Xilinx Vivado 2020.2 on a Kintex-7 device is also included, which proves the hardware complexity reduction and efficiency of the proposed structure.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3425-3435"},"PeriodicalIF":5.2,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ZDD: A Zero Delay Deviation Variability-Aware Golden Free Hardware Trojan Detection Using Physical Unclonable Function 基于物理不可克隆功能的零延迟偏差可变性感知金free硬件木马检测

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-22 DOI: 10.1109/TCSI.2025.3559805

Fakir Sharif Hossain;Ashek Seum;Md. Reasad Zaman Chowdhury;Foisal Ahmed

{"title":"ZDD: A Zero Delay Deviation Variability-Aware Golden Free Hardware Trojan Detection Using Physical Unclonable Function","authors":"Fakir Sharif Hossain;Ashek Seum;Md. Reasad Zaman Chowdhury;Foisal Ahmed","doi":"10.1109/TCSI.2025.3559805","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559805","url":null,"abstract":"Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4153-4166"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Robust Adaptive Control Based on Reduced-Order Unknown Input Observer for Fully Actuated Systems With Uncertainties 不确定全驱动系统基于降阶未知输入观测器的鲁棒自适应控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-22 DOI: 10.1109/TCSI.2025.3559719

Hong Jiang;Guangren Duan;Mingzhe Hou

引用次数: 0

Input Phase Controlled Doherty Power Amplifier With Out-Phased Current Load Modulation for Arbitrary Output Back-Off 输入相位控制的多赫蒂功率放大器，用于任意输出回退的出相电流负载调制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-22 DOI: 10.1109/TCSI.2025.3557496

Bai Hua Zeng;Yu Fei Pan;Fu Cheng Yuan;Wing Shing Chan;Shao Yong Zheng

{"title":"Input Phase Controlled Doherty Power Amplifier With Out-Phased Current Load Modulation for Arbitrary Output Back-Off","authors":"Bai Hua Zeng;Yu Fei Pan;Fu Cheng Yuan;Wing Shing Chan;Shao Yong Zheng","doi":"10.1109/TCSI.2025.3557496","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557496","url":null,"abstract":"A tradeoff between bandwidth and back-off range is commonly found in the Doherty power amplifier (DPA). This paper proposes an input phase control mechanism together with a cooperative asymmetric out-phased current load modulation technique. The cooperative asymmetric out-phased current load modulation can extend the output back-off range (OBO). The input phase control mechanism together with modified impedance transforming load modulation networks (LMNs) is used to widen the DPA bandwidth. An input coupled-line coupler is implemented to realize this phase requirement. For demonstration purposes, a DPA with an operating frequency from 1.7 GHz to 2.9 GHz and with a 9-dB OBO range is designed and fabricated using GaN HEMT devices. Continuous-wave measurements show that the implemented DPA exhibits a drain efficiency ranging from 54.5% to 75.6% at saturation and from 41% to 50.6% at 9-dB OBO across the operating bandwidth. When excited by a 20-MHz long-term evolution (LTE) signal with a 9-dB peak-to-average power ratio (PAPR), the implemented DPA achieves average drain efficiencies of 41%- 53.8% with an adjacent channel leakage ratio (ACLR) better than −48.1 dBc after digital predistortion (DPD).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2626-2638"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Data-Driven Attack Detection and Identification for Cyber-Physical Systems Under Sparse Sensor Attacks: Iterative Reweighted l2/l1 Recovery Approach 稀疏传感器攻击下网络物理系统的数据驱动攻击检测与识别：迭代重加权l2/l1恢复方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-21 DOI: 10.1109/TCSI.2025.3559987

Jun-Lan Wang;Xiao-Jian Li

{"title":"Data-Driven Attack Detection and Identification for Cyber-Physical Systems Under Sparse Sensor Attacks: Iterative Reweighted l2/l1 Recovery Approach","authors":"Jun-Lan Wang;Xiao-Jian Li","doi":"10.1109/TCSI.2025.3559987","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559987","url":null,"abstract":"This paper investigates the data-based attack detection and identification for cyber-physical systems (CPSs) under sparse sensor attacks. In order to improve the identification performance, a novel scheme based on an iterative reweighted <inline-formula> <tex-math>$l_{2}/l_{1}$ </tex-math></inline-formula> minimization algorithm is presented. Firstly, a threshold that characterizes the maximum number of identifiable attacks is determined. By introducing the reweighting technique, smaller weights are assigned to the relatively easy-to-identify attacks, namely, blocks with larger <inline-formula> <tex-math>$l_{2}$ </tex-math></inline-formula>-norms, thus forcing the minimization to focus on the ones with smaller <inline-formula> <tex-math>$l_{2}$ </tex-math></inline-formula>-norms. Then, the number of identifiable attacks is enhanced and a higher identification accuracy is guaranteed compared with the existing results. Finally, three examples are given to verify the effectiveness and advantages of the proposed scheme in both noisy and noiseless cases.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2890-2902"},"PeriodicalIF":5.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling and Nonlinear Dynamic Behavior Analysis of Photovoltaic-Energy Storage DC Microgrid 光伏储能直流微电网建模及非线性动态行为分析

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-21 DOI: 10.1109/TCSI.2025.3558905

Ronglong Wang;Fan Xie;Bo Zhang;Dongyuan Qiu;Wenxun Xiao;Yanfeng Chen

{"title":"Modeling and Nonlinear Dynamic Behavior Analysis of Photovoltaic-Energy Storage DC Microgrid","authors":"Ronglong Wang;Fan Xie;Bo Zhang;Dongyuan Qiu;Wenxun Xiao;Yanfeng Chen","doi":"10.1109/TCSI.2025.3558905","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558905","url":null,"abstract":"In the DC microgrid cluster system, due to the large number of converters, there are many operation modes and switching frequencies. The traditional modeling methods are difficult to balance the accuracy of the model and the simplicity of calculation and are not suitable for different switching frequency systems. In view of the above problems, this paper uses simplified discrete time mapping model to model the system. It combines the state space average model with the discrete time mapping model, which greatly improves the simplicity and accuracy of modeling. Taking the photovoltaic-energy storage system as an example, this paper analyzes the nonlinear behavior of the system and predicts the critical control parameters when the Hopf bifurcation occurs in the system. The eigenvalue sensitivity analysis is used to determine the eigenvalue change rate and change trend when the control parameters change, which provides guidance for the selection of parameters in practical applications. Finally, the high precision of the model is verified by simulation, and the applicability and effectiveness of the method in different switching frequency systems are verified by experiments.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2778-2791"},"PeriodicalIF":5.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Oscillator-Based Reconfigurable Modulator With High-Q FBAR Resonators Supporting Fast OOK/BFSK/ BPSK Modulation 支持快速OOK/BFSK/ BPSK调制的高q FBAR谐振振荡器可重构调制器设计

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-18 DOI: 10.1109/TCSI.2025.3559727

Dong Liang;Hui Zhang;Yetong Wang;Linhao Ma;Shiyue Ma;Zhijun Zhou;Fanyi Meng;Kaixue Ma;Keping Wang

{"title":"Design of Oscillator-Based Reconfigurable Modulator With High-Q FBAR Resonators Supporting Fast OOK/BFSK/ BPSK Modulation","authors":"Dong Liang;Hui Zhang;Yetong Wang;Linhao Ma;Shiyue Ma;Zhijun Zhou;Fanyi Meng;Kaixue Ma;Keping Wang","doi":"10.1109/TCSI.2025.3559727","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559727","url":null,"abstract":"An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2543-2555"},"PeriodicalIF":5.2,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pursuit-Evasion Game for Spacecraft With Incomplete Information Under J₂ Perturbation J 2摄动下不完全信息航天器的追-避博弈

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-18 DOI: 10.1109/TCSI.2025.3560303

Zhenxin Mu;Mingjiang Ji;Pengyu Guo;Qufei Zhang;Bing Xiao;Lu Cao;Junzhi Yu

{"title":"Pursuit-Evasion Game for Spacecraft With Incomplete Information Under J₂ Perturbation","authors":"Zhenxin Mu;Mingjiang Ji;Pengyu Guo;Qufei Zhang;Bing Xiao;Lu Cao;Junzhi Yu","doi":"10.1109/TCSI.2025.3560303","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560303","url":null,"abstract":"In this paper, the dual spacecraft pursuit-evasion game problem under incomplete information is investigated, and a strategy-solving method for the incomplete information pursuit-evasion game based on particle swarm optimization and unscented particle filter (PSO-UPF) estimation is proposed. The completeness of the information available about the target’s cost function, which is determined by the weighting information, has a significant impact on the success of the pursuing strategy. For the cost function is unknown in incomplete information scenarios, a research framework of the pursuit-evasion game based on following observation and one-sided pursuit two stages is established. Besides, to describe the more accurate motion of the spacecraft, a Schweighart-Sedwick (SS) dynamic model is introduced that considers the effect of <inline-formula> <tex-math>$J_{2}$ </tex-math></inline-formula> perturbation. Firstly, an equilibrium strategy for the SS model-based pursuit-evasion problem is derived under complete information. Next, for the incomplete information scenarios, an estimation method based on PSO-UPF of weight matrix information is established, which allows the cost function to be determined by the estimation method in the observation stage. Then, the pursuit strategy is re-designed in the one-sided pursuit stage based on the estimated cost function. Finally, the performance of the proposed method is validated by simulation. The results demonstrate that the approach can achieve good performance by efficiently estimating the weight information in the opponent’s cost function.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4346-4358"},"PeriodicalIF":5.2,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow 基于均衡数据流的轻量级cnn高吞吐量FPGA加速器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-17 DOI: 10.1109/TCSI.2025.3554635

Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu

{"title":"A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow","authors":"Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu","doi":"10.1109/TCSI.2025.3554635","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554635","url":null,"abstract":"FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3338-3351"},"PeriodicalIF":5.2,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency 在奈奎斯特频率下实现54 dB信噪比的28 nm CMOS 3.5 GS/s 11位时交错SAR ADC系统设计

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-17 DOI: 10.1109/TCSI.2025.3559354

Shuai Liu;Yechen Tian;Congyang Sun;Guoyu Li;Hao Xu;Na Yan

引用次数: 0