IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第3页

A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing 基于 RRAM 的神经形态计算的硬件友好型变异容忍框架

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-23 DOI: 10.1109/TCSI.2024.3443180

Fang-Yi Gu;Cheng-Han Yang;Ing-Chao Lin;Da-Wei Chang;Darsen D. Lu;Ulf Schlichtmann

{"title":"A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing","authors":"Fang-Yi Gu;Cheng-Han Yang;Ing-Chao Lin;Da-Wei Chang;Darsen D. Lu;Ulf Schlichtmann","doi":"10.1109/TCSI.2024.3443180","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3443180","url":null,"abstract":"Emerging resistive random access memory (RRAM) attracts considerable interest in computing-in-memory by its high efficiency in multiply-accumulate operation, which is the key computation in the neural network (NN). However, due to the imperfect fabrication, RRAM cells suffer from the variations, which make the values in RRAM cells deviate from the target values so that the accuracy of the RRAM-based NN accelerator degrades significantly. Moreover, in a practical hardware design of RRAM-based NN accelerators, if the number of wordlines and bitlines in a crossbar array activated at the same time increases, ADCs with a high resolution are required and the power consumption of ADC increases. This paper proposes a novel methodology to mitigate the impact of variations in RRAM-based neural network accelerators. The methodology includes a unary-based non-uniform quantization method and a variation-aware operation unit (OU) based framework. The unary-based non-uniform quantization method equalizes the significance of weights stored in each RRAM cell to reduce the impact of variations. The variation-aware OU-based framework activates only RRAM cells in the same OU at the same time, which reduces the power consumption of ADCs. Additionally, the framework introduces three methods, including OU skipping, OU recombination, and OU compensation, to further mitigate the impact of variations. The experiments show that the proposed approach outperforms the state-of-the-art among four NN models on two datasets with 2-bit cell resolution.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6419-6432"},"PeriodicalIF":5.2,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fanout-Based Reliability Model for SER Estimation in Combinational Circuits 用于组合电路 SER 估计的基于扇出的可靠性模型

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3458864

Esfandiar Esmaieli, Yasser Sedaghat, Ali Peiravi

引用次数: 0

Structure-Varying Complex Network Chaotic Model and Its Hardware Implementation 结构变化复杂网络混沌模型及其硬件实现

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3455409

Chenyu Wang, Jun Zheng, Yining Qian

引用次数: 0

Universal Finite-Time Observer-Based ITSMC for Converter-Driven Motor Systems With Disturbances 基于有限时间观测器的通用 ITSMC，适用于有干扰的变频器驱动电机系统

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3457838

Zhongding Zhang, Zeyu Guo, Zuo Wang, Shihua Li

引用次数: 0

An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver 在 28-nm CMOS 有线接收器中使用减少分支最大似然序列检测的自适应 56-Gb/s Duo-PAM4 检测器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-18 DOI: 10.1109/tcsi.2024.3453411

Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang

引用次数: 0

An Automated Fault Attack Framework for Block Ciphers Through Property Mining and Verification 通过属性挖掘和验证的块密码自动故障攻击框架

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-17 DOI: 10.1109/tcsi.2024.3456787

Xingxin Wang, Wei Hu, Shibo Tang, Xinxin Wang, Huisi Zhou

引用次数: 0

Analysis and Design of Wideband Active Single-Sideband Time Modulator in 0.13-$mu$m CMOS 0.13-$mu$m CMOS 宽带有源单边带时间调制器的分析与设计

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-17 DOI: 10.1109/tcsi.2024.3456237

Guoxiao Cheng, Jin-Dong Zhang, Qiaoyu Chen, Wen Wu

引用次数: 0

Offset Boosting-Oriented Construction of Multi-Scroll Attractor via a Memristor Model 通过忆阻器模型构建以偏移升压为导向的多辊吸引器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-16 DOI: 10.1109/tcsi.2024.3455350

Yongxin Li, Chunbiao Li, Sen Zhang, Yuanjin Zheng, Guanrong Chen

引用次数: 0

LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory LLD：针对 3-D TLC NAND 闪存的 LDPC 硬解码轻量级延迟降低方案

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-16 DOI: 10.1109/TCSI.2024.3438789

Debao Wei;Yongchao Wang;Hua Feng;Huqi Xiang;Liyan Qiao

{"title":"LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory","authors":"Debao Wei;Yongchao Wang;Hua Feng;Huqi Xiang;Liyan Qiao","doi":"10.1109/TCSI.2024.3438789","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3438789","url":null,"abstract":"The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4611-4623"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142376906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 $mu$W at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier 采用双斜率时间放大器的 12 ps 精度两步时-数转换器，在 180 nm CMOS 上以 1 MS/s 的速度消耗 434 $mu$W

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-13 DOI: 10.1109/tcsi.2024.3454793

Xinchi Xu, Yonggang Wang, Yonghang Zhou, Zhengqi Song, Bo Wu, Xin Lin

引用次数: 0