IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2025.3541498","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3541498","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1495-1495"},"PeriodicalIF":5.2,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10905059","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2025.3541496","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3541496","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10905062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Theory and Design of Pseudo-Doherty Load-Modulated Double Balanced Amplifier With Intrinsic Insensitivity to Antenna VSWR","authors":"Jiachen Guo;Pingzhu Gong;Kenle Chen","doi":"10.1109/TCSI.2025.3543818","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3543818","url":null,"abstract":"This paper presents a novel Double-Balanced power amplifier (PA) architecture with an intrinsic load isolation. Derived from the generic load modulated balanced amplifier (LMBA), by designing the single-ended control amplifier (CA) as another balanced PA, the Pseudo-Doherty load-modulated double-balanced amplifier (PD-LMDBA) can inherit the intrinsic load-mismatch tolerance of balanced amplifier without any reconfiguration and load-impedance sensing. Theoretical analysis reveals that both the control amplifier (CA, as carrier) and primary balanced amplifier (BA, as peaking) exhibit complementary load modulation trajectories for their sub-amplifiers (CA1 and CA2, BA1 and BA2) under mismatch. This allows the PA to inherit the intrinsic load insensitivity from the generic quadrature-balanced amplifier and sustain nearly constant performance against arbitrary load variations. A prototype is implemented at 2.1 GHz, achieving 76.2% efficiency at peak power and 69.5% at 10-dB OBO with matched load. Under a <inline-formula> <tex-math>$2:1$ </tex-math></inline-formula> voltage standing wave ratio (VSWR) of load mismatch, an efficiency up to 72.5% at peak power and 64.1% at 10-dB OBO are measured. In modulated evaluation with a 20-MHz OFDM signal, the PA maintains linearity against <inline-formula> <tex-math>$2:1$ </tex-math></inline-formula> VSWR, with 2.1% of error vector magnitude (EVM) and down to -39.5 dB adjacent channel power ratio (ACPR), closely approximating the matched condition.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2048-2060"},"PeriodicalIF":5.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Distributed Composite Learning Dynamic Event-Triggered Control for Nonlinear Multi-Agent Power Systems","authors":"Tongxin Shi;Longsheng Chen;Guoyi He;Wei Song","doi":"10.1109/TCSI.2025.3539299","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3539299","url":null,"abstract":"In this paper, a distributed composite learning dynamic event-triggered (ET) control protocol is presented for nonlinear multi-agent power systems (NMAPSs) in the presence of switching topologies, uncertain nonlinearities, external disturbances and limited network resources. A predictor-based continuous emotional self-structuring neural network (NN) is proposed to approximate unknown nonlinearities of NMAPSs. Flexible structure and emotion-based approaches not only can balance the contradiction between computational burden and control performance but also keep a fast response property of NN approximate. The predictor can improve the approximation accuracy and interpretability of NN approximate by introducing a prediction error to update NN’s weights. Next, a dynamic ET mechanism is presented, which introduces a dynamic self-regulation variable to prolong the ET interval. On this basis, the designed control protocol is sent to actuator only at the ET instant to further reduce the network burden. Then, a distributed composite learning control protocol is developed for NMAPSs by utilizing the Lyapunov stability theorem. It can guarantee that all signals in the closed-loop system are bounded under a class of switching topologies with the average dwell time, and the Zeno phenomenon is avoided ultimately. Finally, simulation results are provided to demonstrate the effectiveness of the proposed protocol.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2274-2287"},"PeriodicalIF":5.2,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Quality in Class-D High-Frequency Power Inverter: Input and Resonant Tank Distortion Power, Total Harmonic Distortion, and Power Factor","authors":"Marian K. Kazimierczuk;Fabio Corti;Gabriele Maria Lozito;Alberto Reatti","doi":"10.1109/TCSI.2025.3538106","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3538106","url":null,"abstract":"This paper presents a power quality evaluation of the Class-D high-frequency power amplifier/inverter. The real, reactive, complex, apparent, distortion, and non-active powers at the input of the resonant circuit are derived and illustrated as functions of frequency. Also, the total harmonic distortion and power factor are determined. Similar analysis of the power quality at the dc input of the amplifier is given. Experimental results are given to verify the theory. It is shown that the input current of the Class-D inverter contains a significant ac component that does not contribute to the real dc input power, resulting in high distortion power, high total harmonic distortion, and poor power factor. The Class-D inverter was designed, built and tested to verify the theory.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2419-2431"},"PeriodicalIF":5.2,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ferroelectric FET-Based Bayesian Inference Engine for Disease Diagnosis","authors":"Arka Chakraborty;Musaib Rafiq;Yawar Hayat Zarkob;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/TCSI.2025.3533044","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3533044","url":null,"abstract":"Probabilistic/stochastic computations form the backbone of autonomous systems and classifiers. Recently, biomedical applications of probabilistic computing such as Bayesian networks for disease diagnosis, DNA sequencing, etc. have attracted significant attention owing to their high energy-efficiency. Bayesian inference is widely used for decision making based on independent (often conflicting) sources of information/evidence. A cascaded chain or tree structure of asynchronous circuit elements known as Muller C-elements can effectively implement Bayesian inference. Such circuits utilize stochastic bit streams to encode input probabilities which enhances their robustness and fault-tolerance. However, the CMOS implementations of Muller C-element are bulky and energy hungry which restricts their widespread application in resource constrained IoT and mobile devices such as UAVs, robots, space rovers, etc. In this work, for the first time, we propose a compact and energy-efficient implementation of Muller C-element utilizing a single Ferroelectric FET and use it for cancer diagnosis task by performing Bayesian inference with high accuracy on Wisconsin data set. The proposed implementation exploits the unique drain-erase, program inhibit and drain-erase inhibit characteristics of FeFETs to yield the output as the polarization-state of the ferroelectric layer. Our extensive investigation utilizing an in-house developed experimentally calibrated compact model of FeFET reveals that the proposed C-element consumes (worst-case) energy of 4.1 fJ and an area <inline-formula> <tex-math>$0.07~mu m^{2}$ </tex-math></inline-formula> and outperforms the prior implementations in terms of energy-efficiency and footprint while exhibiting a comparable delay. We also propose a novel read circuitry for realising a Bayesian inference engine by cascading a network of proposed FeFET-based C-elements for practical applications. Furthermore, for the first time, we analyze the impact of cross-correlation between the stochastic input bit streams on the accuracy of the C-element based Bayesian inference implementation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1547-1559"},"PeriodicalIF":5.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.07 pJ/b/dB 36-Gb/s PAM-3 Receiver Using Inductor-Reused CTLE and One-Tap Loop-Unrolled DFE in 22-nm CMOS","authors":"Pin-Yuan Chiu;Shen-Iuan Liu","doi":"10.1109/TCSI.2025.3536091","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3536091","url":null,"abstract":"This paper presents a 36 Gb/s (23.04 GBaud) 3-level pulse amplitude modulation (PAM-3) receiver (RX). The proposed inductor-reused continuous-time linear equalizer (CTLE) uses feedforward and inductive peaking techniques. Additionally, the number of the data slicers is reduced in the PAM-3 receiver with a loop-unrolled decision feedback equalizer (DFE). Furthermore, a baud-rate phase detector (BRPD) is presented. Fabricated in 22-nm CMOS technology, this receiver compensates for a channel loss of 20.5 dB at 11.52 GHz, achieving a bit error rate (BER) of less than <inline-formula> <tex-math>$10^{-12} $ </tex-math></inline-formula> with a pseudo-random ternary sequence (PRTS) of <inline-formula> <tex-math>$3^{7}mathbf {-}1$ </tex-math></inline-formula>. The measured clock integrated jitter is 267 fsrms at 720 MHz, and the retimed data exhibits 10.98 pspp jitter. The overall receiver consumes 51.7 mW, with a calculated energy efficiency of 1.44 pJ/b and a figure of merit (FoM) of 0.07 pJ/b/dB.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1522-1532"},"PeriodicalIF":5.2,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth","authors":"Mohamed Nadeem;Chandan Kumar Jha;Rolf Drechsler","doi":"10.1109/TCSI.2025.3531008","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3531008","url":null,"abstract":"Ensuring functional correctness is achieved through formal verification. As circuit complexity increases, limiting the upper bounds for time and space required for verification becomes crucial. Polynomial Formal Verification (PFV) has been introduced to tackle this problem. In modern digital system designs, approximate circuits are widely employed in error resilient applications. Therefore, ensuring the functional correctness of these circuits becomes essential. In prior works, it has been proven that approximate circuits with constant cutwidth can be verified in linear time. However, extending binary logic verification to Multi-Valued Logic (MVL) introduces challenges, particularly regarding the encoding of MVL operators. It has been shown that MVL circuits with constant cutwidth can be verified in linear time using Answer Set Programming (ASP), due to the ASP encoding capabilities of MVL operators. In this paper, we present a PFV approach of MVL approximate circuits with constant cutwidth using ASP. We then demonstrate that the verification of MVL approximate circuits with constant cutwidth can be achieved in linear time. Finally, we evaluate various MVL approximate circuits with constant cutwidth across different logic levels to show the efficacy of our approach.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1411-1424"},"PeriodicalIF":5.2,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2025.3527913","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3527913","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857687","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2025.3527909","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3527909","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857701","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}