IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第4页

A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow 基于均衡数据流的轻量级cnn高吞吐量FPGA加速器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-17 DOI: 10.1109/TCSI.2025.3554635

Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu

{"title":"A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow","authors":"Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu","doi":"10.1109/TCSI.2025.3554635","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554635","url":null,"abstract":"FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3338-3351"},"PeriodicalIF":5.2,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency 在奈奎斯特频率下实现54 dB信噪比的28 nm CMOS 3.5 GS/s 11位时交错SAR ADC系统设计

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-17 DOI: 10.1109/TCSI.2025.3559354

Shuai Liu;Yechen Tian;Congyang Sun;Guoyu Li;Hao Xu;Na Yan

引用次数: 0

NoCiPUF: NoC-Based Intrinsic PUF for MPSoC Authentication NoCiPUF：基于noc的MPSoC内部PUF认证

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-16 DOI: 10.1109/TCSI.2025.3559419

Deepank Grover;Tarun Sharma;Sneha Agarwal;Sidhartha Sankar Rout;Anushka;Madhur Kumar;Sujay Deb

{"title":"NoCiPUF: NoC-Based Intrinsic PUF for MPSoC Authentication","authors":"Deepank Grover;Tarun Sharma;Sneha Agarwal;Sidhartha Sankar Rout;Anushka;Madhur Kumar;Sujay Deb","doi":"10.1109/TCSI.2025.3559419","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559419","url":null,"abstract":"Modern Multi-Processor-Systems-on-Chips (MPSoCs) use Network-on-Chips (NoCs) as a scalable and efficient communication fabric. The applications running on these devices rely on frequent communication with central database servers, which are vulnerable to impersonation attacks by adversarial clones. We propose NoCiPUF, a novel NoC-based intrinsic Physically-Unclonable-Function (PUF) framework for MPSoCs authentication. We re-use the circuit switched nature of NoC with path-pairs as challenges to obtain secret responses, collectively called challenge-response-pairs (CRPs). Due to the random nature of manufacturing variations, equal hop paths exhibit unequal delays. We leverage the delay differences of flits traversing in equal-hop paths to generate unique responses. NoCiPUF is fully-synthesizable and readily scalable as it requires changes only at the behavioral level. To counter Machine-Learning (ML)-based modeling attacks on PUFs, we provide a comprehensive technique and reduce the prediction accuracy to ~52%. NoCiPUF framework incurs low area (0.76%) and power (1.14%) overheads and has no impact on NoC performance in normal mode due to independent authentication mode. Obtained responses have near-ideal PUF metrics and are verified against the NIST randomness test suite. This scheme offers high number of CRPs in larger NoC networks (>0.74 million CRPs in <inline-formula> <tex-math>$5 times 5$ </tex-math></inline-formula> mesh), proving its scalability.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4167-4180"},"PeriodicalIF":5.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MBS: A High-Precision Approximation Method for Softmax and Efficient Hardware Implementation MBS：一种高精度的Softmax逼近方法和高效的硬件实现

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-16 DOI: 10.1109/TCSI.2025.3559069

Yuanchen Wu;Zhiheng Xie;Hongbing Pan;Yuxuan Wang

{"title":"MBS: A High-Precision Approximation Method for Softmax and Efficient Hardware Implementation","authors":"Yuanchen Wu;Zhiheng Xie;Hongbing Pan;Yuxuan Wang","doi":"10.1109/TCSI.2025.3559069","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559069","url":null,"abstract":"The softmax function needs to be frequently used in the multi-head attention layer of Transformer networks. Compared to DNNs and other networks, Transformers have higher computational complexity, requiring higher accuracy and hardware performance for softmax function calculations. Therefore, we propose mixed-base softmax (MBS) for the first time for the approximation of the softmax function. This method combines exponential functions with bases of 2 and 4, which is advantageous for hardware implementation. MBS has a high similarity to the softmax function and demonstrates advanced performance during inference in Transformer network. Through algorithm transformation and hardware optimization, we have designed a low-complexity and highly parallel hardware architecture, which only occupies few additional hardware resources compared to base-2 softmax but achieves higher accuracy. Experimental results show that, under TSMC 90nm CMOS technology at the frequency of 0.5 GHz, our design can achieve the efficiency of 236.18 Gps/(mm<inline-formula> <tex-math>${^{{2}}} cdot $ </tex-math></inline-formula>mW) with the area of <inline-formula> <tex-math>$4234~mu $ </tex-math></inline-formula>m2. Furthermore, MBS exhibits higher computational accuracy and inference precision compared with base-2 softmax.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3366-3375"},"PeriodicalIF":5.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria 基于级联系统准则的线性异构多智能体系统规定时间协同输出调节新方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-16 DOI: 10.1109/TCSI.2025.3558826

Gewei Zuo;Lijun Zhu;Yujuan Wang;Zhiyong Chen;Yongduan Song

{"title":"A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria","authors":"Gewei Zuo;Lijun Zhu;Yujuan Wang;Zhiyong Chen;Yongduan Song","doi":"10.1109/TCSI.2025.3558826","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558826","url":null,"abstract":"This paper investigates the prescribed-time cooperative output regulation (PTCOR) for a class of linear heterogeneous multi-agent systems (MASs) under directed communication graphs. As a special case of PTCOR, the necessary and sufficient condition for prescribed-time output regulation of an individual system is first explored, whereas only sufficient conditions are developed in the literature. A PTCOR algorithm is subsequently developed, composed of prescribed-time distributed observers, local state observers, and tracking controllers, utilizing a distributed feedforward method. This approach converts the PTCOR problem into the prescribed-time stabilization problem of a cascaded subsystem. The criterion for the prescribed-time stabilization of the cascaded system is proposed, differing from that of traditional asymptotic or finite-time stabilization of a cascaded system. It is proven that the regulated outputs converge to zero within a prescribed time and remain at zero afterward, while all internal signals in the closed-loop MASs are uniformly bounded. Finally, the theoretical results are validated through two numerical examples.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2842-2855"},"PeriodicalIF":5.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Feasibility Condition-Free Approach for Achieving Desired Precision and Unified Performance Within Prescribed Time 一种在规定时间内达到所需精度和统一性能的新颖可行无条件方法

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-15 DOI: 10.1109/TCSI.2025.3552602

Mehdi Golestani;Yongduan Song;Tao Liu;Xiang Xu;Guang-Ren Duan;He Kong

{"title":"A Novel Feasibility Condition-Free Approach for Achieving Desired Precision and Unified Performance Within Prescribed Time","authors":"Mehdi Golestani;Yongduan Song;Tao Liu;Xiang Xu;Guang-Ren Duan;He Kong","doi":"10.1109/TCSI.2025.3552602","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3552602","url":null,"abstract":"This paper proposes a low-complexity tracking control framework for uncertain nonlinear systems in strict feedback and normal forms, respectively. By leveraging a smooth scaling function, these control schemes ensure unified prescribed performance for the output tracking error of strict feedback nonlinear systems and the full-state tracking errors of normal form nonlinear systems. The notion of unified prescribed performance allows for different performance behaviors via performance functions, which can be either constant or time-varying with arbitrarily large initial values. The main contribution is achieving unified prescribed performance for full-state tracking errors without imposing feasibility conditions, a limitation of existing approaches. To eliminate these strict conditions, we introduce a uniform transformation independent of initial conditions. Additionally, the proposed control schemes are low-complexity since they do not require adaptive mechanisms or function approximation to deal with uncertainties and disturbances. The effectiveness of these frameworks is demonstrated through comparative analysis.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2856-2867"},"PeriodicalIF":5.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Fractional Spur Cancellation Technique for Fractional-N Frequency Synthesizers Enabled by Dual Loop Phase Clamping 双环相位箝位的分数n频率合成器的分数杂散抵消技术

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-15 DOI: 10.1109/TCSI.2025.3557837

Tanwei Yan;Junning Jiang;Jose Silva-Martinez

{"title":"A Fractional Spur Cancellation Technique for Fractional-N Frequency Synthesizers Enabled by Dual Loop Phase Clamping","authors":"Tanwei Yan;Junning Jiang;Jose Silva-Martinez","doi":"10.1109/TCSI.2025.3557837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557837","url":null,"abstract":"This paper proposes a fractional spur cancellation technique designed for fractional-N frequency synthesizers. A time domain quantitative analysis is conducted to provide an intuitive understanding of the origin of fractional spurs and to formulate the relationship between the phase error of the feedback signal and the division factor of the frequency divider. By utilizing a dual loop charge-pump based architecture that generates two feedback phases, one leading and one lagging the reference phase, the two loops effectively clamp the reference phase between the two feedback phases and inject complementary charge components to achieve spur reduction. Unlike conventional methods, the proposed analog spur cancellation technique eliminates the need for additional signal processing stages within the loop. This offers several advantages, including reduced complexity, no introduction of additional distortion sources, and minimal impact on loop dynamics. Simulation results employing TSMC 40nm technology demonstrate that the proposed technique can achieve a worst-case fractional spur level of -96.6dBc in a charge-pump based fractional-N frequency synthesizer, offering moderate immunity to mismatches while also slightly improving the phase acquisition time and jitter performance.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3791-3801"},"PeriodicalIF":5.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spurs in Fractional-N Frequency Synthesizers Resulting From Resolution Mismatch Between the Divider Controller and the DTC: Manifestations, Analysis, and Mitigation 分频控制器和DTC之间分辨率不匹配导致的分数n频率合成器中的杂散：表现、分析和缓解

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-14 DOI: 10.1109/TCSI.2025.3557258

Xu Wang;Michael Peter Kennedy

{"title":"Spurs in Fractional-N Frequency Synthesizers Resulting From Resolution Mismatch Between the Divider Controller and the DTC: Manifestations, Analysis, and Mitigation","authors":"Xu Wang;Michael Peter Kennedy","doi":"10.1109/TCSI.2025.3557258","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557258","url":null,"abstract":"The digital-to-time converter (DTC) used in fractional-N phase locked loops is designed to cancel the accumulated quantization error (QE) arising from the divider controller. In high-resolution synthesizers, the DTC performs an additional quantization when mapping the required high-resolution phase correction to its coarse-resolution output. This inherent hard quantization nonlinearity of the DTC, which is different from the DTC’s well-known soft integral nonlinearity, causes yet another kind of inexact cancellation of the QE and induces excess spurious tones that degrade the output phase noise and jitter. This paper reveals the root cause of the “DTC’s QE” and spectral manifestation of the DTC-quantization-induced (DQI) spurs. The waveform of the DTC’s QE is derived analytically; it shows that the DQI-spur pattern is (i) determined by the fractional frequency control word and the quantization resolution of the DTC, and (ii) is independent of the type, order, and modulus of the divider controller. In view of the fact that conventional DTC linearity enhancement techniques and stochastic divider controllers have no effect on DQI-spur mitigation, we propose a novel family of DTC-enhancement methods called input-dithered quantization (IDQ). When used in DTCs, the IDQ methods are effective in eliminating DQI spurs at source with negligible phase noise or jitter penalty.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"2998-3011"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10964399","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2–T Variable Fractional-Spaced FFE in 28-nm CMOS 一个0.92 pj /b的112gb /s PAM-4发射机，具有带宽和线性增强的准电压模式驱动和可重构的三分导T/ 2-T可变分数间隔FFE

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-14 DOI: 10.1109/TCSI.2025.3558331

Ka’Nan Wang;Renjie Tang;Shuyi Xiang;Yukun He;Yunxiang He;Xiaoyan Gui

引用次数: 0

Kolmogorov-Arnold Networks-Based Calibration for Single-Channel ADCs: High-Precision Nonlinear Code Synthesis With Low Power Consumption 基于Kolmogorov-Arnold网络的单通道adc校准：低功耗高精度非线性码合成

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2025-04-14 DOI: 10.1109/TCSI.2025.3555253

Yutao Peng;Xizhu Peng;Hu Wang;Dongbing Fu;Yabo Ni;Can Zhu;Boyuan Zhang;Lei Chen;Zhe Hu;Zhifei Lu;He Tang;Mingqiang Guo

{"title":"Kolmogorov-Arnold Networks-Based Calibration for Single-Channel ADCs: High-Precision Nonlinear Code Synthesis With Low Power Consumption","authors":"Yutao Peng;Xizhu Peng;Hu Wang;Dongbing Fu;Yabo Ni;Can Zhu;Boyuan Zhang;Lei Chen;Zhe Hu;Zhifei Lu;He Tang;Mingqiang Guo","doi":"10.1109/TCSI.2025.3555253","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3555253","url":null,"abstract":"This paper presents a novel calibration scheme for single-channel SAR, pipelined and pipelined-SAR ADCs using Kolmogorov-Arnold networks (KANs). In the proposed scheme, a multi-sample KAN (MS-KAN) is designed to realize nonlinear code synthesis (NLCS), achieving effective calibration for general nonlinear errors. The MS-KAN-based calibrator can be converted into an analytical expression, making the calibration process transparent, with stronger interpretability, predictability and reliability compared to previous neural network-based calibration algorithms, and assisting in the analysis of ADC nonidealities. Meanwhile, the proposed scheme achieves high calibration performance with low hardware overhead. The proposed scheme also requires much fewer training samples, thereby reducing the effort required for both chip testing and network training. The MS-KAN-based calibrator is verified with two silicon-proven ADCs, a 14-bit 1.3 GS/s pipelined ADC and a 10-bit 700MS/s SAR ADC. Measurement results show that SFDR is improved by 11.5 dB to 30.9 dB after calibration. The quantized calibrators are implemented on both FPGA and 28nm CMOS technology, where a piecewise polynomial (PWP) method is adopted to simplify the implementation of the calibrator. The post-layout simulation results show that the calibrator for the real-time calibration of the pipelined ADC consumes only 6.32 mW, while the calibrator for the SAR ADC consumes 2.42 mW.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2497-2508"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0