IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第5页

Q/V-Band CMOS Beamforming ICs and Integrated Phased-Array Antennas Q/V 波段 CMOS 波束成形集成电路和集成相控阵天线

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-05 DOI: 10.1109/tcsi.2024.3450668

Dixian Zhao, Weihan Gao, Ke Li, Hengzhi Wan, Qin Tian, Yongran Yi, Jiajun Zhang, Huiqi Liu

引用次数: 0

Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS 采用 90 纳米 SiGe BiCMOS 设计 64-GBaud 相干互阻抗放大器的信号完整性增强技术

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/TCSI.2024.3450700

Shuaizhe Ma;Nianquan Ran;Xi Liu;Yifei Xia;Songqin Xu;Wei Huang;Chen Tan;Jing Li;Zhenyu Yin;Shaoheng Lin;Jianhua Pan;Zhe Chen;Chaoxuan Zhang;Wu Wen;Quan Pan;Zhongming Xue;Xiaoyan Gui;Li Geng;Dan Li

{"title":"Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS","authors":"Shuaizhe Ma;Nianquan Ran;Xi Liu;Yifei Xia;Songqin Xu;Wei Huang;Chen Tan;Jing Li;Zhenyu Yin;Shaoheng Lin;Jianhua Pan;Zhe Chen;Chaoxuan Zhang;Wu Wen;Quan Pan;Zhongming Xue;Xiaoyan Gui;Li Geng;Dan Li","doi":"10.1109/TCSI.2024.3450700","DOIUrl":"10.1109/TCSI.2024.3450700","url":null,"abstract":"This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between \u0000<inline-formula> <tex-math>$150~Omega $ </tex-math></inline-formula>\u0000 - 5 K\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5221-5234"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ImSTDP: Implicit Timing On-Chip STDP Learning ImSTDP：隐式定时片上 STDP 学习

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3450958

Dedong Zhao, Oliver Schrape, Zoran Stamenkovic, Milos Krstic

引用次数: 0

Lipschitz Stability Estimate for an Initial Wave Reconstruction Problem of Telegraph Type With Gaussian Noise 有高斯噪声的电报型初始波重建问题的 Lipschitz 稳定性估计

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3451505

Dat-Thuc Nguyen, Ngoc Tuan Duong, Vo Anh Khoa

引用次数: 0

A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces 一种单端 PAM-4 发射器，使用无堆叠无台阶 CML 驱动器和用于存储器接口的系数校正 FFE

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/TCSI.2024.3450875

Yong-Un Jeong;Joo-Hyung Chae

{"title":"A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces","authors":"Yong-Un Jeong;Joo-Hyung Chae","doi":"10.1109/TCSI.2024.3450875","DOIUrl":"10.1109/TCSI.2024.3450875","url":null,"abstract":"This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter using an unstacked tailless current-mode logic (CML) driver for memory interfaces. Compared with the voltage-mode (VM) driver commonly used for single-ended memory interfaces, the proposed CML driver has stable termination for impedance matching and a small pre-driver with low dynamic power consumption, which allow the transmitter to achieve a higher data rate and a better total energy efficiency. The unstacked driver structure with an auxiliary leg and a current calibration scheme leads to high PAM-4 linearity by compensating for channel-length modulation that causes current source variation while occupying a small area. The strength of the feed-forward equalization (FFE) distorted by channel-length modulation is also compensated by an additional pulse of the proposed coefficient-corrected equalization. A prototype chip fabricated in a 65-nm CMOS process has an area of 0.0172 mm\u0000<inline-formula> <tex-math>$^{2}{}$ </tex-math></inline-formula>\u0000. It achieves a data rate of 34 Gb/s/pin with an energy efficiency of 0.60 pJ/bit and a level separation mismatch ratio (RLM) of 0.987.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6306-6315"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Throughput LDPC Decoder for Multiple Wireless Standards 适用于多种无线标准的高吞吐量 LDPC 解码器

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3419425

Wei Chen, Yajie Li, Dake Liu

引用次数: 0

Distributed Resilient Secondary Control for AC Microgrids Against Hybrid Attacks 针对混合攻击的交流微电网分布式弹性二级控制

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/TCSI.2024.3449896

Jianwen Zhang;Sha Fan;Chao Deng;Bohui Wang;Xiangpeng Xie

引用次数: 0

Firefly: A Versatile Experimental Platform for Oscillator-Based Ising Machines 萤火虫：基于振荡器的伊辛机的多功能实验平台

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/TCSI.2024.3448531

Markus Graber;Klaus Hofmann

{"title":"Firefly: A Versatile Experimental Platform for Oscillator-Based Ising Machines","authors":"Markus Graber;Klaus Hofmann","doi":"10.1109/TCSI.2024.3448531","DOIUrl":"10.1109/TCSI.2024.3448531","url":null,"abstract":"Oscillator-based Ising machines (OIMs) are specialized in solving combinatorial optimization problems, that can be represented as the Ising model. They exploit the interaction of (integrated) electrical oscillators in a configurable network for the computation. Such systems naturally evolve towards a ground state, which forms a solution to the problem quickly and energy efficiently. This work presents the design of our 400 oscillator node chip in a 28nm technology. The focus is on the analog oscillator and coupler circuits, which determine the computing performance. Weighted optimization problems with up to 6-bit resolution can be solved within just 714ns. A comprehensive experimental analysis based on a versatile benchmark set is provided. We discuss the computation process and investigate the impact of multiple factors including the randomness of the initial oscillator phases, the frequency mismatch, the coupling strength, and the locking strength. A small range of parameters like the coupling strength and locking strength exists, which show the highest accuracy. Extensive benchmarks achieve an accuracy compared to the best-known solution of more than 94.5% for problems with equal weights and 89.8% for weighted problems. This emphasizes, that carefully designed oscillator-based Ising machines (OIMs) are not only fast, but can find solutions near the global optimum.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5944-5955"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Energy-Efficient Capacitive-RRAM Content Addressable Memory 高能效电容式 RAM 内容寻址存储器

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/TCSI.2024.3451707

Yihan Pan;Adrian Wheeldon;Mohammed Mughal;Shady Agwa;Themis Prodromakis;Alexantrou Serb

{"title":"An Energy-Efficient Capacitive-RRAM Content Addressable Memory","authors":"Yihan Pan;Adrian Wheeldon;Mohammed Mughal;Shady Agwa;Themis Prodromakis;Alexantrou Serb","doi":"10.1109/TCSI.2024.3451707","DOIUrl":"10.1109/TCSI.2024.3451707","url":null,"abstract":"Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a \u0000<inline-formula> <tex-math>$64times 64$ </tex-math></inline-formula>\u0000 array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take three clock cycles. Its worst average energy for data match is reported to be 1.71fJ/bit-search and the worst average energy for data miss is found at 4.69fJ/bit-search. The prototype is simulated and fabricated in 0.18um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5285-5295"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping 具有二阶噪声整形功能的 3.5 GS/s 1-1 MASH VCO ADC

IF 5.1 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI: 10.1109/tcsi.2024.3450570

Brendan Saux, Jonas Borgmans, Johan Raman, Pieter Rombouts

引用次数: 0