IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3494637","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494637","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6584-6584"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact Reconfigurable Dual-Band MMIC SPDT/SP4T Switches With On-Chip Coupled-Line Structure in GaN-on-SiC HEMT Technology","authors":"Xu Yan;Jingyuan Zhang;Baoguo Yang;Si-Ping Gao;Yongxin Guo","doi":"10.1109/TCSI.2024.3504273","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3504273","url":null,"abstract":"This paper presents the design and analysis of dual-band monolithic microwave integrated circuit (MMIC) switches, including a single pole double throw (SPDT) and a single pole four throw (SP4T). With a novel on-chip coupled-line (OCL) topology, the input signal can be switched into low- or high-band paths to create dual-band characteristics. By carefully selecting the electrical lengths of OCLs and device size for corresponding shunt-FETs, the operating frequencies for low- and high-bands can be determined. This brings about improved insertion loss (IL) and isolation (ISO) in a compact structure. With the proposed techniques, two switch prototypes have been designed and fabricated in a 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaN-on-SiC process for high-power capability. The SPDT consists of a low-band path and a high-band path. It achieves an average IL/ISO of 1.0/32 dB with the best input 1-dB compression points (IP1dB) of 37.2 dBm at a low-band of DC-15 GHz; and an average IL/ISO of 2.0/28.5 dB with the best IP1dB of 32.8 dBm at a high-band of 20-40 GHz, respectively. The return loss is better than 11 dB for each port. The SP4T achieves a fully integrated dual-band transmit/receive (T/R) switch with doubled low-/high-band paths. It shows an average IL/ISO of 2.26/27.5 dB with the best IP1dB of 31.2 dBm at a low-band of 5-15 GHz; and an average IL/ISO of 2.7/26.5 dB with the best IP1dB of 30 dBm at a high-band of 20-30 GHz have been achieved, respectively. Better than 11.3 dB return loss is obtained for each port. The chip sizes are <inline-formula> <tex-math>$1.8times 0.9$ </tex-math></inline-formula> mm2 for the SPDT and <inline-formula> <tex-math>$2.2times 1.7$ </tex-math></inline-formula> mm2 for the SP4T.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1029-1041"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editorial Special Issue on the International Symposium on Circuits and Systems—ISCAS 2024","authors":"Xinmiao Zhang","doi":"10.1109/TCSI.2024.3494892","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494892","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5375-5375"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3494635","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494635","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768278","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3494639","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494639","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768430","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A SPAD Image Sensor With Main-Sub-TDC-Based Coincidence Detection","authors":"Chenggong Wan;Yi Zhu;Yingjie Ma;Xue Li;Lixia Zheng;Jin Wu;Weifeng Sun","doi":"10.1109/TCSI.2024.3503422","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3503422","url":null,"abstract":"Light detection and ranging (Lidar) is usually enabled by Single-Photon Avalanche Detector (SPAD) sensors which may be falsely triggered by ambient light. Coincidence detection can suppress the ambient light at the cost of the lateral resolution. A \u0000<inline-formula> <tex-math>$64times 64$ </tex-math></inline-formula>\u0000 SPAD image sensor with coincidence detection is proposed for Lidar. A main-sub time-to-digital converter (TDC), in which the main TDC is used for timestamping the coincidence window and the sub-TDC is used for timestamping the event within the coincidence window, is proposed to avoid the loss of the lateral resolution at a small power cost. A delay-locked loop (DLL) is adopted to generate an analog voltage for maintaining the length of the coincidence window against process-voltage-temperature (PVT) variations. A TDC code correction circuit is proposed to reduce the probability of TDC inter-segment errors to 0.7%. The SPAD image sensor is based on the 3D integration of a SPAD array with a ROIC. The ROIC chip is fabricated in a \u0000<inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>\u0000m CMOS process. Driven by a 250 MHz multi-phase clock and a 100 MHz data readout clock, the chip achieves a maximum frame rate of 35.7 kframe/s, a timing resolution of 0.5 ns, and a timing range of \u0000<inline-formula> <tex-math>$2mu $ </tex-math></inline-formula>\u0000s. The typical average power consumption of the ROIC is 135.5 mW (@21.7 kframes/s). The measured differential nonlinearity (DNL) ranges from -0.74 to +0.82 least significant bit (LSB), and the integral nonlinearity (INL) ranges from -0.95 to +0.95 LSB.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"50-60"},"PeriodicalIF":5.2,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Back-Gate Bias Control on EVM Measurements of a Dual-Band Power Amplifier in 22 nm FD-SOI for 5G 28 and 39 GHz Applications","authors":"Lucas Nyssens;M. Nabet;M. Rack;Y. Bendou;S. Wane;J. B. Sombrin;J.-P. Raskin;D. Lederer","doi":"10.1109/TCSI.2024.3487636","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3487636","url":null,"abstract":"This paper presents a dual-band power amplifier (PA) covering the 5G n257 to n260 frequency 2 bands (24.25 to 29.5 GHz and 37 to 43.5 GHz), fabricated in the 22 nm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Its design is based on a distributed balun at the output that efficiently performs a wideband load impedance transformation. The back-gate terminal of each transistor is connected to different pads for detailed back-gate bias variation analysis. Under 5G new radio (NR) modulated signal measurements, we show how the average output power and efficiency can be optimized by varying the back-gate bias, which optimal value depends on (i) the signal bandwidth, (ii) the carrier frequency and (iii) the target error-vector-magnitude (EVM) value. To the best of the authors’ knowledge, the impact of back-gate bias control on the system-level EVM figure of merit is shown for the first time in this work. Overall, with 7.5 dBm and 7.3% mean output power and efficiency, respectively, at 27 GHz, 6 dBm and 5% at 40 GHz, for a 800 MHz bandwidth 5G NR signal, the presented PA shows outstanding performance among wideband/multiband FD-SOI-based PAs covering the 28 and 39 GHz bands, featuring comparable performance to best-in-class narrowband PA designs in FD-SOI technology.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"753-762"},"PeriodicalIF":5.2,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Mitigation of Excess Phase Noise and Spurs in Digital-to-Time-Converter-Enhanced Fractional- N Frequency Synthesizers","authors":"Xu Wang;Michael Peter Kennedy","doi":"10.1109/TCSI.2024.3501998","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3501998","url":null,"abstract":"Digital-to-time converters (DTC’s) used in fractional-N phase locked loops (PLL’s) aim to zero the quantization error (QE) introduced by the divider controller in order to recover integer-N phase noise (PN) performance. Unfortunately, the inherent quantization behavior and integral nonlinearity associated with the DTC mean that the aforementioned QE cannot be canceled exactly; inevitably, the residual error gives rise to additional PN and spurious tonal phenomena. This tutorial paper uses DTC macromodels to analyze and distinguish the DTC’s sources of nonideality and the distinct adverse spectral responses induced by them. Different DTC enhancement techniques are shown to mitigate certain types of nonideality. A comprehensive design strategy incorporating these techniques is proposed, which mitigates the revealed excess PN and spurs introduced by the DTC’s nonidealities. The enhanced DTC enables the fractional-N DPLL to approach the fractional-spur-free integer-N PN performance limit. Behavioral simulations at both DTC-block and PLL-system levels confirm our analysis.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1042-1055"},"PeriodicalIF":5.2,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10762790","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Design Method for CML Frequency Divider Based on C/Id and G/Id and Application for Quadrature-Injection CML Frequency Dividers","authors":"Leilei Xiao;Yubing Li;Haifeng Chen;Yujia Chen;Zemeng Huang;Peng Ke;Xiuping Li","doi":"10.1109/TCSI.2024.3500017","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3500017","url":null,"abstract":"A novel design method for current-mode-logic (CML) frequency divider based on <inline-formula> <tex-math>${C/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${G/I} _{boldsymbol {d}}$ </tex-math></inline-formula> is proposed. The design method proposes using <inline-formula> <tex-math>${C/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${G/I} _{boldsymbol {d}}$ </tex-math></inline-formula> as independent design parameters, where C and G are the equivalent capacitance and conductance of coupling pair (C cell) and negative-<inline-formula> <tex-math>$boldsymbol {g}_{boldsymbol {m}}$ </tex-math></inline-formula> pair (N cell) in CML frequency dividers. Different from the traditional design method optimizing the maximum operating frequency (<inline-formula> <tex-math>$boldsymbol {f}_{textit {in,max} }$ </tex-math></inline-formula>) by adjusting the self-resonant frequency (<inline-formula> <tex-math>$boldsymbol {f}_{textit {SR} }$ </tex-math></inline-formula>), the proposed design method directly targets <inline-formula> <tex-math>$boldsymbol {f}_{textit {in,max} }$ </tex-math></inline-formula> and output amplitude (<inline-formula> <tex-math>$boldsymbol {V}_{textit {out} }$ </tex-math></inline-formula>) to obtain the <inline-formula> <tex-math>${C/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${G/I} _{boldsymbol {d}}$ </tex-math></inline-formula> and solve the size and bias current of C and N cells, which realizes efficient design. Based on the proposed design method, several design examples are provided showing less than 3% error between the simulation results and design goals, and the proposed quadrature-injection CML (QI-CML) frequency divider is implemented and proven to have an improved sensitivity curve (SC). To validate the efficacy of our proposal, a frequency divider that can switch between differential-injection (DI) and QI is designed and fabricated in 110-nm CMOS process. For QI mode, the measured locking range (LR) is 141% (5-29 GHz) while consuming 5.47 mW. The achieved two figure of merits FOM<inline-formula> <tex-math>$_{textbf {Pdc}}$ </tex-math></inline-formula> and FOM<inline-formula> <tex-math>$_{textbf {A}}$ </tex-math></inline-formula> are 24.1 dB and 52.8 dB, respectively, which are superior to most published works.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1140-1151"},"PeriodicalIF":5.2,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3-D Multi-Precision Scalable Systolic FMA Architecture","authors":"Haotian Liu;Xicheng Lu;Xiaoyu Yu;Kai Li;Kaiyuan Yang;Haihang Xia;Sizhao Li;Tiantai Deng","doi":"10.1109/TCSI.2024.3497724","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3497724","url":null,"abstract":"Artificial Intelligence (AI) has almost become the default approach in a wide range of applications, such as computer vision, chatbots, and natural language processing. These AI-based applications require computing large-scale data with sufficient precision, typically in floating-point numbers, within a limited time window. A primary target for AI acceleration is matrix multiplication, mainly involving dot products through Multiply-Accumulate (MAC) operations. Current research employs the Fused Multiply-Add (FMA) operation, based on IEEE-754 Floating Point (FP) standard, to meet these requirements. However, current research focuses more on simplifying the internal digital circuits of the Processing Elements (PEs) performing FMA operations, rather than optimizing the FMA process specifically for MAC tasks. Current PE arrays often use a two-dimensional (2-D) systolic array design, without specific optimization for MAC operations, thus their parallelism is not fully utilized. Additionally, these designs lack reconfigurability and flexibility, leading to suboptimal performance on Field-Programmable Gate Arrays (FPGAs). Moreover, some designs adopt lower precision computing in AI inference for higher performance. However, some AI models still rely on high-precision computing to maintain the accuracy. Thus, multi-precision computing is commonly used in AI accelerators. To address these challenges, this paper proposes a novel Multi-Fused Multiply-Accumulate (MFMA) scheme and a corresponding three-dimensional (3-D) scalable systolic FP computing architecture. The MFMA scheme addresses the problem of the classical FMA scheme. It optimizes FMA for MAC operations with the Fused Multiply-Accumulate (FMAC) operation. Also, it combines multi-precision and mixed-precision FP computing methods for higher accuracy and lower overflow error. The proposed architecture integrates two 2-D systolic arrays into the PE for a 3-D systolic array, achieving higher parallelism and flexibility. The proposed scalable architecture can be customized to suit various FMAC operations. Compared with existing state-of-the-art FP architectures on FPGAs, our proposed architecture achieves 47%, 10%, and 159% energy efficiency improvements in FP32, FP16, and INT8 operations, respectively. Furthermore, our proposed architecture achieves energy efficiency improvements of 105%, 54%, and 262% under efficiency saturation conditions, outperforming the existing state-of-the-art design.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"265-276"},"PeriodicalIF":5.2,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}