IEEE Transactions on Circuits and Systems I: Regular Papers最新文献_第5页

FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-19 DOI: 10.1109/TCSI.2024.3511383

Morgana Macedo Azevedo da Rosa;Leonardo Antonietti;Rodrigo Lopes;Eloisa Barros;Eduardo Antonio Ceśar da Costa;Rafael Soares

{"title":"FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders","authors":"Morgana Macedo Azevedo da Rosa;Leonardo Antonietti;Rodrigo Lopes;Eloisa Barros;Eduardo Antonio Ceśar da Costa;Rafael Soares","doi":"10.1109/TCSI.2024.3511383","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3511383","url":null,"abstract":"This work proposes an integrated framework for accuracy and logic synthesis (LS) estimation of approximate adders (FALSAx). It represents a versatile and robust framework designed to estimate the accuracy, power, and area of various approximate adders (AxAs) for any input width (W) and K bits of approximation using machine learning (ML) models. FALSAx facilitates performance predictions and optimization for different AxAs configurations through meticulously curated datasets and ML-driven analysis. The framework’s capability to automatically generate Pareto fronts from estimated values aids in identifying optimal trade-offs among crucial metrics, providing essential insights for circuit design and optimization. The FALSAx includes four internal frameworks: FrAQ, PILSE, and FELSE, which estimates dynamic power, total leakage power, and area, with frequency variations automatically, and the FALED dataset of the FALSAx. As a case study, this work analyzed 16 types of AxAs on FALSAx: AMA-V, AxPPA, COPY, TRUNC, ETA, LOA, HOERAA, LDCA, LZTA, HEAA, M-HEAA, HERLOA, M-HERLOA, HOAANED, OLOCA, and SETA. The rigorous analysis provided by FALSAx revealed that HERLOA, M-HERLOA, M-HEAA, and AxPPA demonstrated superior accuracy metrics such as SSIM, NCC, MAE, and MRE. Furthermore, power analysis showed that AxPPA exhibited the best power efficiency for lower approximation bits (<inline-formula> <tex-math>$K leq 3$ </tex-math></inline-formula>). At the same time, gate-free adders like COPY, TRUNC, AMA-V, LDCA, and LZTA were more power-efficient for higher approximation bits (<inline-formula> <tex-math>$K gt 3$ </tex-math></inline-formula>). Area estimations indicated that AxPPA maintained competitive efficiency for lower approximation bits (<inline-formula> <tex-math>$K leq 5$ </tex-math></inline-formula>), while TRUNC and LDCA were more efficient for higher bits (<inline-formula> <tex-math>$K gt 5$ </tex-math></inline-formula>).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1679-1692"},"PeriodicalIF":5.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-19 DOI: 10.1109/TCSI.2024.3518462

Jianhang Yang;Rong Zhou;Xianlong Xiong;Linwei Wang;Hongjian Lan;Shubin Liu;Zhangming Zhu

{"title":"A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application","authors":"Jianhang Yang;Rong Zhou;Xianlong Xiong;Linwei Wang;Hongjian Lan;Shubin Liu;Zhangming Zhu","doi":"10.1109/TCSI.2024.3518462","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3518462","url":null,"abstract":"In this paper, we present an ultra-low power wake-up receiver (WuRX) with effective interference suppression capability. A specific robust design has been implemented to address the common interference issues in the industrial, scientific, and medical (ISM) frequency band. A mathematical expression is derived in this paper for the minimum signal-to-noise ratio (SNR) required by the comparator at which a envelope detector first (ED-first) WuRX can detect the wake-up message in the presence of interference. Aiming to meet the minimum SNR requirements, a quasi-direct coupling (QDC) baseband buffer scheme is proposed. Compared to the output SNR of traditional AC schemes, the QDC baseband buffer scheme achieves a 4.16 dB increase in output SNR under optimal conditions. To solve the problem where traditional comparator calibration schemes require recovery time after sudden disappearance of interference, the multipath signal detection (MPSD) scheme proposed in this paper can immediately detect information following the disappearance of interference, which improves detection efficiency. The WuRX is manufactured in 65nm LP process, consuming 7.56nW at a 0.4V power supply, with a sensitivity of −79dBm in the 433MHz ISM band. Under continuous wave (CW) interference, the receiver achieves a signal-to-interference ratio (SIR) of −31dB at a frequency offset of 1MHz.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1878-1887"},"PeriodicalIF":5.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Memristor-Based Parallel Computing Circuit Optimization for LSTM Network Fault Diagnosis

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-17 DOI: 10.1109/TCSI.2024.3516325

Junwei Sun;Yuhan Cao;Yi Yue;Shiping Wen;Yanfeng Wang

{"title":"Memristor-Based Parallel Computing Circuit Optimization for LSTM Network Fault Diagnosis","authors":"Junwei Sun;Yuhan Cao;Yi Yue;Shiping Wen;Yanfeng Wang","doi":"10.1109/TCSI.2024.3516325","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3516325","url":null,"abstract":"Researchers often focus on algorithmic enhancements while overlooking the potential benefits of hardware improvements. In this paper, a memristor-based parallel computing circuit optimization for LSTM network fault diagnosis is proposed. In response to the slow convergence of the algorithm, the characteristics of the memristor can matrix the algorithm and import it into the hardware circuit. The amnesia parallelization strategy executes four iterative processes simultaneously. The convergence speed is improved. Using the high-speed capability of the amnesia in parallel matrix operations using memristive circuits, four circuit modules are designed:mutation, crossover, evolution, and selection. These modules are integrated into a memristor circuit network model. To efficiently complete the iterative process and make effective use of the memristor’s strong storage property, the best-fit values are stored. To validate the effectiveness of the algorithm, simulations and comparative experiments are conducted on the Case Western Reserve University (CWRU) dataset. The results show that the model optimised with memristor hardware circuitry has improved the accuracy by 98% and has better fault diagnosis performance. This research not only advances the integration of memristive devices in neural network optimization, showcasing significant implications for the design of advanced circuit systems in the era of intelligent computing.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"907-917"},"PeriodicalIF":5.2,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Inverse Proportional Chaotification Model for Image Encryption in IoT Scenarios 物联网场景下图像加密的反比例混沌化模型

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-11 DOI: 10.1109/TCSI.2024.3511675

Wenhao Liu;Kehui Sun;Huihai Wang;Binglun Li;Yongjiu Chen

{"title":"Inverse Proportional Chaotification Model for Image Encryption in IoT Scenarios","authors":"Wenhao Liu;Kehui Sun;Huihai Wang;Binglun Li;Yongjiu Chen","doi":"10.1109/TCSI.2024.3511675","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3511675","url":null,"abstract":"In Internet of Things (IoT) scenarios, the limited computing resources and energy constraints of devices, alongside the growing demand for real-time applications, make secure image transmission challenging. To address this issue, we propose a lightweight image encryption scheme based on chaotic map. Firstly, a new 3-D inverse proportional chaotic map (3D-IPCM) is designed with good robustness. Dynamics confirms that it possesses key characteristics, including a broad and continuous chaotic range, all positive Lyapunov exponents (LEs), high permutation entropy (PE) complexity and even distribution. Then, a new pseudorandom number generator (PRNG) is designed based on this map, which successfully passes all NIST and TestU01 tests, even with 16-bit calculation precision. Next, this PRNG is employed for image encryption in IoT scenarios. In the cryptosystem, a chromosome crossover (CC)-based scrambling algorithm is proposed, along with a diffusion algorithm that achieves strong resistance to differential attack in just two rounds of row diffusion. Simulation and analysis verify that the cryptosystem has strong resistance to common attacks and low cost. For \u0000<inline-formula> <tex-math>$256 times 256$ </tex-math></inline-formula>\u0000 images, its average number of pixels change rate (NPCR) and unified average changing intensity (UACI) are 100% and 33.40%, respectively, and the encryption time is only 7.4 ms. Ultimately, we implement the algorithm on FPGA, thus confirming its capacity for parallel acceleration.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"254-264"},"PeriodicalIF":5.2,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Correct and Verify—CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-11 DOI: 10.1109/TCSI.2024.3509013

Chandan Kumar Jha;Khushboo Qayyum;Muhammad Hassan;Rolf Drechsler

{"title":"Correct and Verify—CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits","authors":"Chandan Kumar Jha;Khushboo Qayyum;Muhammad Hassan;Rolf Drechsler","doi":"10.1109/TCSI.2024.3509013","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3509013","url":null,"abstract":"Approximate adders have received significant attention as they give benefits in power, performance, and area for error-resilient applications. Due to their ubiquitous use, formal verification of approximate adders has also gained traction. However, prior works on formal verification of approximate adders are limited to relaxed equivalence checking, i.e., checking whether the approximate adder designs have an error less than a specified threshold. This method has limitations, as multiple approximate adder designs can satisfy the relaxed equivalence checking criterion, which can cause more than expected deterioration in the output quality. The deterioration in output quality is larger in approximate adder designs that produce exact results for some regions of the input space but have the freedom to produce approximate results in other regions of the input space. In this paper, we propose a methodology called Correct and Verify (CAV), which exploits Binary Decision Diagrams (BDDs) to guarantee that the approximate adder with correct carry bits exactly matches its functional specification. Our idea takes advantage of the BDD structure in extracting the internal signals, particularly the carry signal from the golden reference exact adder. Afterward, a corrector circuit is generated from the functional specification and the extracted carry signal is used as input in the corrector circuit. The corrector circuit is used to generate the corrected adder from the approximate adder. The generated corrected adder can be compared against a formally verified golden reference exact adder. We show the efficacy of CAV over approximate Ripple Carry Adders (RCA) as well as approximate Parallel Prefix Adders (PPA). Lastly, we perform a qualitative analysis by introducing mutations in the designs to show the fault detection quality of the CAV methodology.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1718-1730"},"PeriodicalIF":5.2,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-11 DOI: 10.1109/TCSI.2024.3512366

Naveed Ishraq;Ayan Mallik

{"title":"Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter","authors":"Naveed Ishraq;Ayan Mallik","doi":"10.1109/TCSI.2024.3512366","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3512366","url":null,"abstract":"In this paper, the small signal model for a four-level flying capacitor multilevel (FCML) totem-pole PFC converter is presented. In contrast to conventional PFC converters, the state space equations for the FCML PFC converter in a complete switching cycle change over the line cycle. If the standard state space averaging technique is applied, it will only evaluate a single combination of state space equations corresponding to only one segment of the line cycle. Since the four-level FCML PFC converter consists of three different segments in one half-line cycle, this technique is not applicable to derive a comprehensive small signal model of the converter that is required for regulation and transient stability. Moreover, the effects of flying capacitors on the FCML PFC dynamics are nulled out using the average model due to their natural balancing capability. In this work, the Fourier analysis of time-interval modulated switched network is used to determine the closed form small-signal control to output frequency response and verify its accuracy with the experimental results. The dynamic characteristic of the FCML converter is also evaluated for the variations in the converter passive elements. Finally, a hardware prototype is designed, fabricated, and tested for ac input 120 Vac, 400-V dc output, and 1-kW power rating demonstrating peak efficiency of 98.48%, power factor 0.995 and THD of 4.26% to observe the system behavior under load step changes.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1926-1938"},"PeriodicalIF":5.2,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Predicting Higher-Order Dynamics With Unknown Hypergraph Topology

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-11 DOI: 10.1109/TCSI.2024.3513406

Zili Zhou;Cong Li;Piet Van Mieghem;Xiang Li

{"title":"Predicting Higher-Order Dynamics With Unknown Hypergraph Topology","authors":"Zili Zhou;Cong Li;Piet Van Mieghem;Xiang Li","doi":"10.1109/TCSI.2024.3513406","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3513406","url":null,"abstract":"Predicting future dynamics on networks is challenging, especially when the complete and accurate network topology is difficult to obtain in real-world scenarios. Moreover, the higher-order interactions among nodes, which have been found in a wide range of systems in recent years, such as the nets connecting multiple modules in circuits, further complicate accurate prediction of dynamics on hypergraphs. In this work, we proposed a two-step method called the topology-agnostic higher-order dynamics prediction (TaHiP) algorithm. The observations of nodal states of the target hypergraph are used to train a surrogate matrix, which is then employed in the dynamical equation to predict future nodal states in the same hypergraph, given the initial nodal states. TaHiP outperforms three latest Transformer-based prediction models in different real-world hypergraphs. Furthermore, experiments in synthetic and real-world hypergraphs show that the prediction error of the TaHiP algorithm increases with mean hyperedge size of the hypergraph, and could be reduced if the hyperedge size distribution of the hypergraph is known.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1693-1706"},"PeriodicalIF":5.2,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-11 DOI: 10.1109/TCSI.2024.3509634

Lida Xu;Zewen Cao;Hualong Zhao;Zhuo Peng;Yuchi Miao;Chunan Zhuang;Hongrui Ruan;Yuying Dong;Chuanbin Zeng;Bo Li;Jiajun Luo

{"title":"RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification","authors":"Lida Xu;Zewen Cao;Hualong Zhao;Zhuo Peng;Yuchi Miao;Chunan Zhuang;Hongrui Ruan;Yuying Dong;Chuanbin Zeng;Bo Li;Jiajun Luo","doi":"10.1109/TCSI.2024.3509634","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3509634","url":null,"abstract":"Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end iteration cycle and cost of processor chip development are too high, and cannot flexibly respond to changes in chip fragmented design specifications. 2) Processor chip verification is less agile, and there is a lack of a full-chain processor agile design platform that can be easily ported to different development environments. To tackle both issues, we propose an object-oriented hardware agile design methodology, oriented by time, cost, and complexity, and have built the RIVL platform to support the agile development process for processors. RIVL integrates a highly automated design flow for processor RTL design, Integration, Verification, and Layout design to improve processor development efficiency. We achieved tape-out verification of more than 60 RISC-V processors through agile design methods, demonstrating the use and effectiveness of RIVL. We quantify the performance of CoreGen using CoreMark and demonstrate that CoreGen achieves industry-competitive performance.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1668-1678"},"PeriodicalIF":5.2,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-09 DOI: 10.1109/TCSI.2024.3506828

Prashansa Mukim;Gabriella A. Carini;Hucheng Chen;Grzegorz W. Deptuch;Shanshan Gao;Gianluigi De Geronimo;Soumyajit Mandal;Venkata Narasimha Manyam;Veljko Radeka;Sergio Rescia

{"title":"Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals","authors":"Prashansa Mukim;Gabriella A. Carini;Hucheng Chen;Grzegorz W. Deptuch;Shanshan Gao;Gianluigi De Geronimo;Soumyajit Mandal;Venkata Narasimha Manyam;Veljko Radeka;Sergio Rescia","doi":"10.1109/TCSI.2024.3506828","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3506828","url":null,"abstract":"This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89K. The chip was fabricated in a 180nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77K, indicate that the channel outputs have high linearity (INL <0.1%)> <tex-math>$mu $ </tex-math></inline-formula>s and a detector capacitance of 150pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1496-1509"},"PeriodicalIF":5.2,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10783050","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications

IF 5.2 1区工程技术

IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-12-09 DOI: 10.1109/TCSI.2024.3507783

Chen Deng;Sai Wu;Chengcheng Liu;Yatao Peng;Man-Kay Law;Jun Yin;Rui P. Martins;Pui-In Mak

{"title":"A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications","authors":"Chen Deng;Sai Wu;Chengcheng Liu;Yatao Peng;Man-Kay Law;Jun Yin;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSI.2024.3507783","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3507783","url":null,"abstract":"Cryo-CMOS IC for quantum applications, proposed for tens of years, are designed to control quantum processors operating at cryogenic temperatures (CTs). The reference circuits play a significant role in quantum controllers, providing a relatively stable biasing for analog and radio frequency (RF) circuit blocks. Based on a literature review, we discovered that achieving high-accuracy reference voltage or current at CTs is challenging due to the unstable temperature characteristics of complementary metal-oxide-semiconductor (CMOS), bipolar junction transistor (BJT), or resistors in the general CMOS process at CTs. Therefore, certain specialized device structures, such as dynamic threshold MOS (DTMOS), can be employed within the bulk CMOS process. Alternatively, BJT and other devices found in specific processes, such as silicon-germanium (SiGe) and fully depleted silicon on insulator (FD-SOI) CMOS, can achieve adaptive temperature compensation. This paper provides a succinct overview of several fundamental structures and common research hot spots about the reference voltage circuits, and then assesses their suitability for CT circuit design, considering the reliability of devices in bulk CMOS, FD-SOI CMOS, and SiGe process. Finally, the paper summarizes the types of cryo-temperature reference circuits and offers an overview and comparison of them.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1533-1546"},"PeriodicalIF":5.2,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0