IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"Fixed-Time Generalized VGESO-Based Trajectory Tracking Control for WMRs on Uneven Road: A Fully Actuated System Approach","authors":"Jiaping Qiang;Li Li;Changchun Hua;Xiangyi Ren;Chao Liu","doi":"10.1109/TCSI.2025.3560091","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560091","url":null,"abstract":"In this paper, a trajectory tracking control problem is investigated for a wheeled mobile robot (WMR) on uneven road. A mapping relationship is established between the velocity and position to describe the motion of the robot on uneven road. An adaptive kinematic controller (AKC) is designed to improve the trajectory tracking accuracy, where robot parameters and control gains are both estimated. Then, a fixed-time generalized variable gain extended state observer (VGESO) is proposed to estimate the states and disturbance caused by uneven road, where a balance is maintained between disturbance rejection and noise suppression. Next, a dynamic controller is put forward by combining fully actuated system (FAS) approach with practical prescribed time (PPT) control. It is analyzed that the velocity tracking error system is PPT stable. Finally, experimental results demonstrate effectiveness and superiority of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2915-2927"},"PeriodicalIF":5.2,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization","authors":"Xujiang Xiang;Zhiheng Yue;Xiaolong Zhang;Shaojun Wei;Yang Hu;Shouyi Yin","doi":"10.1109/TCSI.2025.3547001","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547001","url":null,"abstract":"Deep neural networks (DNNs) have brought about a transformative impact across various sectors. However, the proliferation of DNNs has led to a surge in computational intensity and data traffic, thereby imposing substantial demands on the power capacity and battery life of computing systems. Computing-in-memory (CIM) is considered a promising architecture to resolve or mitigate the memory wall challenge by integrating computational elements within memory arrays. Yet prior studies on CIM have seldom capitalized on sparsity in both activations and weights simultaneously. Furthermore, the exploitation of two-sided sparsity—sparsity in both activations and weights—presents new challenges, such as imbalanced workload and low hardware substrate utilization. To harness the full potential of two-sided sparsity for acceleration, we present Dyn-Bitpool, an accelerator that introduces innovations on two fronts: 1) a balanced workload scheme, “pool first and cross lane sharing”, which maximizes performance gains enabled by the bit-level sparsity in activations; and 2) a dynamic topology for CIM arrays to effectively address the low CIM macro utilization issue caused by the value-level sparsity in weights. These collective advancements yield an average speedup of 1.91x and 2.67x for Dyn-Bitpool on eight prevalent neural networks, outperforming two cutting-edge CIM-based accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2216-2228"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Circuit Transfer Matrix: A Novel Approach to Enhancing Circuit Analysis Efficiency by Extending the Transfer Matrix Method for Multibody System","authors":"Zhan Jin;Xiao-Ting Rui;Fu-Feng Yang","doi":"10.1109/TCSI.2025.3531876","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3531876","url":null,"abstract":"To address the challenge of high computational complexity in large-scale circuit analysis, the Circuit Transfer Matrix Method is proposed, drawing on the strong parallels between electrical and mechanical systems. This method builds upon the Transfer Matrix Method for Multibody Systems, which has seen significant breakthroughs and widespread use in complex mechanical systems, extending its application to circuit analysis. Unlike traditional model-reduction techniques, the circuit transfer matrix method employs the concepts of ‘transfer’ of system state vectors and the ‘assembly’ of transfer matrices, effectively reducing the order of the system’s equations and significantly improving computational efficiency. This reduced-order model allows designers to analyze and synthesize a system’s dynamic behavior within a limited design cycle more efficiently. The text presents the computational workflow of the Circuit Transfer Matrix Method, from the definition of state vectors to the invocation and assembly of transfer matrices, followed by the solution of the transfer equations. The fundamental component transfer matrices are derived upon which the method for deriving the transfer matrices of combined elements is provided, along with a corresponding example. Subsequently, examples are provided to illustrate the detailed computational processes for linear AC analysis, transient analysis of linear chain systems, transient analysis of linear closed-loop systems, and transient analysis of general nonlinear systems. The accuracy of the algorithm is validated by comparisons with methods based on SPICE. Finally, a comparison of the algorithm speed with SPICE reveals that SPICE has an asymptotic time complexity of <inline-formula> <tex-math>$O(n^{3})$ </tex-math></inline-formula>, while the Circuit Transfer Matrix Method has a complexity of only <inline-formula> <tex-math>$O(n)$ </tex-math></inline-formula>, significantly enhancing computational efficiency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2804-2817"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"First Demonstration of Power-Linear Regulator for Thermo-Optic Phase Tuning","authors":"Yuhang Wang;Da Ming;Xiaofei Chen;Bing Li;Min Tan","doi":"10.1109/TCSI.2025.3549722","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549722","url":null,"abstract":"This paper presents a power-linear regulator (PLR) using a voltage-squaring feedback loop designed for linear thermo-optic tuning. Nonlinear phase tuning occurs when conventional digital-to-analog converters (DACs) or low-dropout regulators (LDOs) are used to drive the thermo-optic phase shifter since the introduced phase change is proportional to the square of the voltage. The nonlinear phase tuning introduces the distortion and non-uniform resolution which degrades the system performance. We propose a PLR to achieve linear thermo-optic phase tuning, where the phase change is proportional to the input voltage. By adopting a voltage-squaring feedback loop, the output voltage is proportional to the square-root of the input voltage under fixed resistive heater and a linear mapping between the input voltage and phase change is established. This design is fabricated in a standard CMOS 65 nm process with an active area of 0.014 mm2. Under 2.5 V supply voltage, the proposed design achieves an input range of <inline-formula> <tex-math>$0sim 1$ </tex-math></inline-formula> V and corresponding output range of <inline-formula> <tex-math>$0sim 2$ </tex-math></inline-formula> V. The maximum delivered power is up to 40 mW while driving a <inline-formula> <tex-math>$100~Omega $ </tex-math></inline-formula> load. The measured power linearity error is <inline-formula> <tex-math>$3.5~%$ </tex-math></inline-formula>. Additionally, the design demonstrates rapid transient behavior under a <inline-formula> <tex-math>$100~Omega $ </tex-math></inline-formula> load, with <inline-formula> <tex-math>$0.2~mu $ </tex-math></inline-formula>s rise time and <inline-formula> <tex-math>$0.7~mu $ </tex-math></inline-formula>s fall time between 0 mW output power and 40 mW output power. The line regulation is 6 mV/V under <inline-formula> <tex-math>$100~Omega $ </tex-math></inline-formula> load. To the best of our knowledge, it is the first PLR demonstrated in the literature.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2039-2047"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Structure-Reconfigurable Wide Gain Series Resonant Converter for On-Board Charger","authors":"Deyu Wang;Xianpeng Chen;Qinglin Zhao;Zbigniew Kaczmarczyk","doi":"10.1109/TCSI.2024.3505271","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3505271","url":null,"abstract":"In this article, a structure-reconfigurable series resonant DC-DC converter is proposed for a wide gain on-board charger application. The proposed converter consists of a dual-bridge structure on the primary side which can realize 0.5 to 1 voltage gain by using a reconfigurable half/full bridge structure, and a hybrid rectifier on the secondary side which can realize 1 to infinite voltage gain by replacing two diodes with active switches. Moreover, the proposed converter employs a control scheme based on fixed frequency PWM, with the operating frequency being identical to the series resonant frequency. Accordingly, magnetizing inductance of the transformer is independent of the converter gain characteristics, which simplifies the consideration of the resonance parameters design. In addition, soft switching can be realized during the entire charging process, and high efficiency can be achieved. To avoid the voltage spike and current impact in the transition between two operation modes, a unified switching modulation strategy is applied to achieve a smooth transition and improve the control stability. Finally, a 2.5 kW prototype with an output voltage range of 200V - 500 V is established and tested to verify the effectiveness and feasibility of the proposed converter.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 4","pages":"1951-1961"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Topkima-Former: Low-Energy, Low-Latency Inference for Transformers Using Top-k In-Memory ADC","authors":"Shuai Dong;Junyi Yang;Xiaoqi Peng;Hongyang Shang;Ye Ke;Xiaofeng Yang;Hongjie Liu;Arindam Basu","doi":"10.1109/TCSI.2025.3549060","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3549060","url":null,"abstract":"Transformer has emerged as a leading architecture in neural language processing (NLP) and computer vision (CV). However, the extensive use of nonlinear operations, like softmax, poses a performance bottleneck during transformer inference and comprises up to 40% of the total latency. Hence, we propose innovations at the circuit, algorithm and architecture levels to accelerate the transformer. At the circuit level, we propose Topkima—combining top-<italic>k</i> activation selection with in-memory ADC (IMA) to implement efficient softmax without any sorting overhead. Only the <italic>k</i> largest activations are sent to softmax calculation block, reducing the huge computational cost of softmax. At the algorithmic level, a modified training scheme utilizes top-<italic>k</i> activations only during the forward pass, combined with a sub-top-<italic>k</i> method to address the crossbar size limitation by aggregating each sub-top-<italic>k</i> values as global top-<italic>k</i>. At the architecture level, we introduce a fine pipeline for efficiently scheduling data flows and an improved scale-free technique for removing scaling cost. The combined system, dubbed Topkima-Former, enhances <inline-formula> <tex-math>$1.8times -84times $ </tex-math></inline-formula> speedup and <inline-formula> <tex-math>$1.2times -36times $ </tex-math></inline-formula> energy efficiency (EE) over prior In-memory computing (IMC) accelerators. Compared to a conventional softmax macro and a digital top-<italic>k</i> (Dtopk) softmax macro, our proposed Topkima softmax macro achieves about <inline-formula> <tex-math>$15times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> faster speed respectively. Experimental evaluations demonstrate minimal (0.42% to 1.60%) accuracy loss for different models in both vision and NLP tasks.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2509-2519"},"PeriodicalIF":5.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology","authors":"Qi Mao;Shi Li;Guobao Liu;Liqian Dou;Bailing Tian;Qun Zong","doi":"10.1109/TCSI.2025.3539893","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3539893","url":null,"abstract":"In this article, we deliver analytical expressions to characterize the attainable consensusability of a linear unstable multi-agent system (MAS). The considered MAS undergoes uncertainty variations and non-minimum phase dynamics, whose interaction topology is delineated by a communication network with a directed spanning tree. Our primary objective is to compute the maximal robustness consensus margins, which can clearly describe how communication network connectivity, the control protocols, and the system's dynamics exert influences on allowable robustness consensus in the framework of output feedback control. Towards this aim, we resolve the robust consensus problem along the spirit of the gain and phase margin problems, which amounts to handling two constrained optimization problems over feasible regions based on the stability analysis theorem of the MAS characteristic polynomials. We finally formulate explicit conditions and analytical expressions of achieved robustness consensus margins, wherein the results show the restrictions of the agent's unstable pole, non-minimum phase zero, and network connectedness on the robustly achieved gain and phase consensus margins.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2481-2481"},"PeriodicalIF":5.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10929757","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impedance Circuit Model of Voltage Source Converter With DC-Link Voltage Control Dynamics","authors":"Zhen Wang;Peng Cheng;Hao Pan;Limin Jia","doi":"10.1109/TCSI.2025.3548907","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3548907","url":null,"abstract":"The impedance circuit model maps the control algorithms into the circuit topology of voltage source converters (VSCs). By analyzing discrete circuit elements, the model provides clear physical insight for the oscillation mechanisms triggered by the control dynamics. However, previous studies do not consider the outer-loop control and reactive power. To enhance the generality, this paper integrates the DC-link voltage control (DVC) loop into the impedance circuit model and thoroughly considers the non-unity power factor operating conditions. In this model, DVC dynamics is mapped as two equivalent impedances in the AC circuit, and interaction between the inner and outer loops is visualized by the interconnection of impedances. The analysis indicates that the perturbation of DVC dynamics on grid-connected current introduces the negative resistance effect at low-power levels. Moreover, the effect of reactive power on impedance circuit is mapped as a coupled current source linking the d-axis and q-axis circuits. As the inductive-reactive power increases, self-excited oscillations occur in the coupled source. According to the stability constraints of the coupled sources, a strict design method for the control parameters is proposed. Experimental results verify the effectiveness of the proposed model.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2970-2983"},"PeriodicalIF":5.2,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Data-Based Output Containment of Completely Heterogeneous Multi-Agent Systems With Unknown Dynamics and Its Application","authors":"Shicheng Huo;Zhipeng Wang;Hao Shen;Ya Zhang;Chao Deng","doi":"10.1109/TCSI.2025.3547894","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547894","url":null,"abstract":"In this paper, a data-based containment control method is proposed for multi-agent systems where the system parameters of both leaders and followers are <italic>heterogeneous</i> and <italic>unknown</i>. Based on the collected data from the leader systems, the least square method is first utilized to identify the parameters of the leaders. Then, the data-based adaptive distributed compensator is designed for each follower to estimate the system parameters and the states of the <italic>heterogeneous</i> leaders. Meanwhile, the collected data from follower systems is used to construct the local observer and establish the data-based linear matrix inequalities to determine the observer gains and feedback gains. On the basis of the collected data from leader and follower systems, the data-based adaptive solutions to the output regulation equations are provided. Furthermore, the data-based containment control protocols are designed to realize that the outputs of the followers converge to the convex hull formed by the unknown heterogeneous leaders. Finally, the effectiveness of the proposed data-based control scheme is illustrated by the simulation of the numerical example and the interconnecting RLC circuits.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2903-2914"},"PeriodicalIF":5.2,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer","authors":"Xiangqu Fu;Jinshan Yue;Muhammad Faizan;Zhi Li;Qiang Huo;Feng Zhang","doi":"10.1109/TCSI.2025.3561245","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3561245","url":null,"abstract":"Multimodal Transformer (MMT) algorithms have become the state-of-the-art for multimodal tasks such as image captioning. The Encoder-Decoder (E-D) structure, consisting of Encoder, Decoder-causal, and Decoder-cross components, provides a flexible and effective framework for multimodal tasks. However, previous accelerators mainly focus on the dataflow and hardware optimization of the Encoder, which fails to accelerate the entire E-D structure efficiently. There remain three challenges: 1) the lack of pipeline and multicore optimization at the module, layer, and E-D level; 2) the Decoder-causal and Decoder-cross computations have lower arithmetic intensity compared to the Encoder, requiring a better solution for the varying arithmetic intensities; and 3) the autoregressive algorithm in Decoder-causal leads to redundant KV Cache accesses and considerable idle power. In this paper, <italic>SHMT</i>, an SRAM and HBM hybrid computing-in-memory (CIM) architecture, is designed to efficiently support multimodal Transformers with three key contributions: 1) a multi-level pipelined multicore scheme, including pipeline optimization across E-D layer-head-module levels and a multicore network-on-chip (NoC) architecture, to reduce inference latency and off-chip accesses; 2) a heterogeneous SRAM-HBM architecture, utilizing high-density HBM-CIM for low-arithmetic-intensity (LAI) parts and high-performance SRAM-CIM for high-arithmetic-intensity (HAI) parts; and 3) by integrating KV Cache with zero-padding in SRAM-CIM, SHMT eliminates redundant read-write operations in KV Cache, reducing idle power consumption. Experiment results show that SHMT achieves <inline-formula> <tex-math>$212times $ </tex-math></inline-formula> speedup, reduces energy consumption by <inline-formula> <tex-math>$208times sim 2000times $ </tex-math></inline-formula> per token, and achieves <inline-formula> <tex-math>$13.3times $ </tex-math></inline-formula> higher energy efficiency compared to NVIDIA A100 GPU.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2712-2725"},"PeriodicalIF":5.2,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}