IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"A Dual Slope Boosted Relaxation Oscillator With 2.93 μJ/Cycle Energy Efficiency and 0.068% Period Jitter in 180 nm CMOS","authors":"Yongjuan Shi;Xun Liu;Chen Hu;Xiyuan Tang;Junmin Jiang","doi":"10.1109/TCSI.2025.3557560","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557560","url":null,"abstract":"This paper presents a 2MHz relaxation oscillator designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (FIA) is adopted such that 1) the requirement of comparator speed is significantly alleviated and 2) the power consumption of the amplifier is further reduced. The proposed relaxation oscillator was fabricated in a 180nm CMOS process and occupies only 0.1mm² active area. The measurement results with 8 samples show that the average power consumption is <inline-formula> <tex-math>$2.93mu $ </tex-math></inline-formula>J/cycle (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W/MHz) at 1V supply voltage at room temperature. The average standard variation of the period jitter is 345ps, which is 0.068% of 500ns typical oscillation period (<inline-formula> <tex-math>$T_{mathrm {OSC}}$ </tex-math></inline-formula>). The measured temperature coefficient is 128ppm/°C within the 0 to 90°C range, and the voltage variation is 0.74%/0.1V from 0.95V to 1.15V. It scores a high phase noise figure-of-merit of 148dBc/Hz at 10kHz offset frequency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2520-2528"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Inductor Current Ripple Minimization in PV-Fed Modular Multilevel DC-DC Converter With Distributed MPPT Control","authors":"V. Sukanya;G. V. Sumesh;S. J. Lohit Prakash;B. Bijukumar","doi":"10.1109/TCSI.2025.3558367","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558367","url":null,"abstract":"Modular multilevel DC-DC converters find extensive use in power electronics due to their utilization of a single inductor, the potential for serial connection of N number of sub-modules (SMs), and a modular design. Recent research indicates that minimizing ripple in inductor current is feasible by maintaining a fixed interleaving angle of <inline-formula> <tex-math>$frac {100}{N}$ </tex-math></inline-formula> % between the SMs during equal duty ratio operating conditions. This study explores the application of these converters in photovoltaic (PV) systems incorporating individual maximum power point tracking (MPPT) control. In this context, individual MPPT control imposes varied duty ratio conditions on the SMs, arising from differences in the sources of each SM, especially in instances of partial shading condition (PSC). This variability can potentially influence the current ripple within the system. This article conducts a thorough theoretical analysis to derive the optimal interleaving angle criteria for minimizing current ripple under conditions of unequal duty ratios. Additionally, a control strategy is proposed to integrate angle optimization with MPPT control based on the derived conditions. Further, it is observed that operating the converter at this optimal angle leads to a significant reduction in ripple current, by a factor of at least <inline-formula> <tex-math>$frac {1}{N}$ </tex-math></inline-formula>. The MATLAB/PLECS simulations and experimental results verify considerable improvements in ripple reduction compared to the conventional interleaving angle method, both during steady-state and PSC.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4389-4402"},"PeriodicalIF":5.2,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Power-Efficient Active-RC Filter Using Passive Integrator and OTA With Push-Pull Output","authors":"Liangbo Lei;Cong Tao;Zhipeng Chen;Zhiliang Hong;Yumei Huang","doi":"10.1109/TCSI.2025.3554894","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554894","url":null,"abstract":"This paper presents a power-efficient fourth-order, 50-MHz active-RC filter with high dynamic range (DR). Unlike conventional Tow-Thomas biquads, the proposed design employs a passive integrator as the second pole to reduce power consumption, enhance noise performance, and facilitate frequency compensation. The active integrator features a two-stage operational transconductance amplifier (OTA) with a push-pull output, ensuring linearity and reducing the OTA’s gain requirements. Fabricated in standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology, the proposed filter achieves an in-band (IB) input third-order intercept point (IIP3) of +29.9 dBm at 30 MHz and an input-referred IB integrated noise of <inline-formula> <tex-math>$163.8~mu $ </tex-math></inline-formula>VRMS, while consuming 5.4 mW for a 50-MHz bandwidth.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5314-5324"},"PeriodicalIF":5.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient FPGA Implementation of Multi-Channel Pipelined Large FFT Architectures Based on SA-MDF Algorithm","authors":"Tang Hu;Chunling Hao;Xier Wang;Zhiwei Liu;Songnan Ren;Zhiwei Xu;Shiqiang Zhu","doi":"10.1109/TCSI.2025.3547003","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3547003","url":null,"abstract":"FPGA implementation of a multi-channel pipelined large FFT architecture is challenging due to its complex inter-channel data scheduling, high-throughput requirement, and resource-constrained hardware. By transforming to 2D-FFT implementation, investigating different binary tree schemes, and exploring various radices, butterflies, as well as data path structures, many hardware architectures have been designed to enhance single-channel large FFT or multi-channel medium-small size FFT performance. These designs fall short in addressing the demands of multi-channel pipelined and large FFT applications. In this article, a self-attention multipath delay feedback (SA-MDF) algorithm is proposed to analyze and identify the most critical bottleneck, then automatically pay attention to improve it, and finally generate the optimal FFT framework by exhaustively exploring the design space. The proposed algorithm alleviates the design difficulties and speeds up the FPGA implementation. Furthermore, an approximate roofline model and a novel binary tree scheme are introduced to further minimize the utilization of on-chip memory. A comprehensive comparison in terms of principles, implementation methods, and optimization effects is conducted when compared with other multi-channel FFT architectures. Experimental results show that the proposed FFT architectures are superior to other FFT implementations in terms of channel count, FFT length, high-throughput data arrangement, and adaptability to diverse hardware platforms.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2189-2201"},"PeriodicalIF":5.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing","authors":"P. J. Zhou;R. C. Ma;Y. C. Chen;Z. T. Liu;C. Y. Liu;L. W. Meng;G. C. Qiao;Y. Liu;Q. Yu;S. G. Hu","doi":"10.1109/TCSI.2025.3557955","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557955","url":null,"abstract":"The transformer model has demonstrated significant capabilities in various intelligent tasks, attracting widespread attention in recent years. However, it involves numerous complex operations, including large-bit-width multiplication, division, matrix transposition, and exponentiation. These require substantial storage and computational resources, making it challenging to deploy on edge devices. This work introduces a neuromorphic transformer architecture with low hardware cost for AI edge computing (AI-EC). At the structural level, it absorbs scaling factors within the self-attention mechanism into weight matrixes, thereby eliminating the division caused by the scaling operation. Additionally, a transposition calculation method is proposed to perform matrix transposition using dedicated memory access strategies and optimized data flow designs, which reduces logic resource overhead and avoids memory access discontinuities. At the computing paradigm level, the architecture employs spike-driven computing, substituting multi-bit multipliers with AND logic for synaptic operations. The paradigm introduces high sparsity to computational data, which is effectively exploited to reduce the computational workload of the architecture. The results indicate that the architecture successfully eliminates high-cost operators and significantly reduces computational expenses. Eventually, this architecture is verified as a prototype using a 28 nm CMOS process library, demonstrating a compact logic area of sub-0.2 mm² and a high energy efficiency of 0.34 pJ/SOP @ 50MHz. This work is expected to promote the application of transformers in edge computing and the development of intelligent edge applications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2676-2689"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multi-Stage RC Compensation Technique for Decoupling the Transimpedance and BW: Creating High Speed and Low Noise TIA Designs","authors":"Muhammad Bilal Babar;Gordon W. Roberts","doi":"10.1109/TCSI.2025.3556802","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3556802","url":null,"abstract":"The gain and bandwidth of a shunt-feedback Transimpedance Amplifier (TIA) is limited by a so called transimpedance (TI) limit. This limit dictates the maximum possible value of the feedback resistance (<inline-formula> <tex-math>$R_{F}$ </tex-math></inline-formula>) for a targeted bandwidth. Additionally, the input referred noise of such TIAs is inversely proportional to the <inline-formula> <tex-math>$R_{F}$ </tex-math></inline-formula>, which presents a challenge in simultaneous optimization of bandwidth, noise and transimpedance gain. In this paper, the TI limit is revisited, and a multi-stage RC compensation technique is presented for the design of the open-loop amplifier for a closed-loop shunt-feedback-based TI stage. This paper shows that with the appropriate pole-zero positioning, the DC transimpedance gain can be decoupled from the closed-loop TI bandwidth. This is achieved by placing a zero in the open loop transfer function to reduce the impact of the closed loop dominant pole created by the input capacitance and the RF. As a result, without the need for area consuming inductors, a TI stage is realized which has a transimpedance limit that is larger than the conventionally assumed limit. Additionally, the proposed RC compensation network provides more control over the pole-zero positioning which results in smooth overall frequency response after equalization. This is verified by experimental results which show that the proposed technique achieves a much greater transimpedance gain as compared to that of the conventional limit while reducing the noise and without any significant deterioration of bandwidth. The design has been implemented in a 90 nm BiCMOS process from Global Foundries (GF-9HP). A detailed comparison of the proposed approach is presented with other TIA designs. As per the author’s best knowledge, the proposed design outperforms the state-of-the-art TIA designs in terms of the noise-transimpedance-bandwidth trade-off.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3847-3860"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10962192","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Unified Sampled-Data Small-Signal Model for a Ripple-Based COT Buck Converter With Arbitrary Ripple Injection Network","authors":"Francesco Gabriele;Antonio Carlucci;Davide Lena;Fabio Pareschi;Riccardo Rovatti;Stefano Grivet-Talocia;Gianluca Setti","doi":"10.1109/TCSI.2025.3557278","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557278","url":null,"abstract":"In this paper, we present a novel and unified small-signal modeling technique for Pulse-Width Modulated (PWM) DC-DC Buck converters with Ripple-Based Constant On-Time (RBCOT) control. In fact, despite the spread of RBCOT-based converters in several applications requiring tight dynamic performances and a low architectural complexity, their description through small-signal models is not always as reliable as that of fixed-frequency PWM control architectures, and a general and exact modeling framework is not well established. The proposed methodology is grounded on the DC-DC converter state-space representation and thus, differently from other modeling techniques, it permits to fully characterize the dynamic behavior of generic RBCOT converter topologies with arbitrary complex power stage and ripple injection networks. As a case study, we derive the small-signal model for a Buck converter embedding a widely used ripple injection network in industrial applications. The validity of the theoretical results is confirmed through direct comparison with SIMetrix/SIMPLIS simulations and experimental measurements in practical application scenarios, confirming the accuracy of the model even well beyond the converter switching frequency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2942-2955"},"PeriodicalIF":5.2,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Four-Port Probe Calibration Using 64-Term Error Model for On-Wafer S-Parameter Measurement of Microwave Circuits Up to 110 GHz","authors":"Jiefeng Zhou;Ling Zhang;Ziyang Chen;Da Li;Jun Fan;Er-Ping Li","doi":"10.1109/TCSI.2025.3544672","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3544672","url":null,"abstract":"This article presents a novel four-port probe calibration method for on-wafer S-parameter measurement of microwave circuits and, for the first time, realizes measurement verification up to 110 GHz. The method regards the 64 error terms in the four-port probe calibration as an error matrix, which can be solved by a homogeneous equation system using a generalized scatter matrix theory. The calibration algorithm can consider the crosstalk between the probes and improve the calibration accuracy at high frequencies. This method only requires six calibration standards to complete the four-port probe calibration. Only one coupled differential line with a symmetric structure is needed as the Thru, which replaces the traditional U-shape and asymmetric Thru and effectively reduces the number of calibration standards used in the four-port probe calibration. In addition, the method combined with an optimization method accurately and efficiently calculates the parasitic parameters of the calibration standards at high frequencies. The proposed method is validated by three different devices under test (DUTs) up to 110 GHz. Their S-parameters obtained by the proposed method, including all the pure-mode and mode-conversion terms, have high accuracy in magnitude and phase, proving the correctness and convenience of this method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5471-5481"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rational-Exponent Filters with Applications to Generalized Exponent Filters","authors":"Samiya A. Alkhairy","doi":"10.1109/TCSI.2025.3545459","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3545459","url":null,"abstract":"We present filters with rational exponents in order to provide a continuum of filter behavior not classically achievable. We discuss their stability, the flexibility they afford, and various representations useful for analysis, design and implementations. We do this for a generalization of second-order filters which we refer to as rational-exponent Generalized Exponent Filters (GEFs) that are useful for a diverse array of applications. We present equivalent representations for rational-exponent GEFs in the time and frequency domains: transfer functions, impulse responses, and integral expressions - the last of which allows for efficient real-time processing without preprocessing requirements. Rational-exponent filters enable filter characteristics to be on a continuum rather than limiting them to discrete values thereby resulting in greater flexibility in the behavior of these filters without additional complexity in causality and stability analyses compared with classical filters. In the case of GEFs, this allows for having arbitrary continuous rather than discrete values for filter characteristics such as 1) the ratio of 3dB quality factor to maximum group delay - particularly important for filterbanks which have simultaneous requirements on frequency selectivity and synchronization; and 2) the ratio of 3dB to 15dB quality factors that dictates the shape of the frequency response magnitude.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 5","pages":"2139-2152"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143888363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Observability Verification System Analysis for Observability and Reconstructibility of Probabilistic Logical Control Networks","authors":"Yalu Li;Haitao Li;Gaoxi Xiao","doi":"10.1109/TCSI.2025.3553463","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3553463","url":null,"abstract":"Observability and reconstructibility are two fundamental issues in modern control theory, which are important in both state estimation and observer design. The existing results for verifying the observability and reconstructibility of probabilistic logical control networks (PLCNs) have exponential complexities. This article presents a new approach to verify the observability and reconstructibility of PLCNs, which can greatly reduce the computational complexity. Specifically, the problem is tackled in three different steps. Firstly, based on the division of the state pair space, an observability verification system is established. Secondly, the equivalence between the stabilization of the proposed observability verification system and the observability of PLCNs is revealed, and a new criterion is established to solve the observability of PLCNs. Under the framework, the computational complexity is discussed. Thirdly, the relationship between observability and reconstructibility of PLCNs is unveiled, and some new criteria are established to solve two kinds of reconstructibility problems for PLCNs. Finally, an example of a biological network, apoptosis network, is presented to demonstrate the feasibility of the methods proposed in this article.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4273-4283"},"PeriodicalIF":5.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}