Shuai Liu;Yechen Tian;Congyang Sun;Guoyu Li;Hao Xu;Na Yan
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引用次数: 0
摘要
本文提出了一种针对时间交错SAR ADC的面向设计的分析方法,该方法量化了不同的缺陷来源,以提供统一的设计框架。这包括单通道和交错缺陷。为了验证该理论的有效性,在28nm CMOS工艺下设计并制作了一个时间交错ADC原型。通过一次性前景时序倾斜和偏移补偿,3.5 GS/s 11位时间交错SAR ADC在低输入频率下可实现55.6 dB SNDR,在奈奎斯特频率下可实现54.3 dB SNDR,而在1v电源下功耗为66.0 mW,其中时钟缓冲功率为14.8 mW。
Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency
This paper presents a design-oriented analysis for the time-interleaved SAR ADC that quantifies different sources of imperfections to provide a unified design framework. This includes both single-channel and interleaving imperfections. A prototype time-interleaved ADC is designed and fabricated in a 28 nm CMOS process to validate the effectiveness of the theory. With one-time foreground timing skew and offset compensation, the 3.5 GS/s 11-bit time-interleaved SAR ADC achieves 55.6 dB SNDR at low input frequency and 54.3 dB SNDR at Nyquist frequency while dissipating 66.0 mW at 1 V supply including 14.8 mW clock buffer power.
期刊介绍:
TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.